Searched refs:irqstatus (Results 1 - 14 of 14) sorted by path

/u-boot/arch/arm/include/asm/arch-omap3/
H A Ddss.h42 u32 irqstatus; /* 0x18 */ member in struct:dss_regs
55 u32 irqstatus; /* 0x18 */ member in struct:dispc_regs
/u-boot/arch/arm/mach-omap2/
H A Dmem-common.c169 writel(0x00000000, &gpmc_cfg->irqstatus);
/u-boot/drivers/mtd/nand/raw/
H A Domap_elm.c112 while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
115 writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
116 &elm_cfg->irqstatus);
H A Domap_elm.h62 u32 irqstatus; /* 0x018 */ member in struct:elm
/u-boot/drivers/ram/k3-ddrss/
H A Dlpddr4.c52 bool irqstatus = false; local
59 result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
60 } while ((irqstatus == (bool)false) && (result == (u32)0));
69 bool irqstatus = false; local
76 result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
77 } while ((irqstatus == (bool)false) && (result == (u32)0));
473 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus) argument
478 result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
483 *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
H A Dlpddr4_am6x.c168 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) argument
175 result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
186 *irqstatus = true;
189 *irqstatus = true;
191 *irqstatus = false;
H A Dlpddr4_am6x_sanity.h19 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
21 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
29 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) argument
35 } else if (irqstatus == NULL) {
163 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) argument
169 } else if (irqstatus == NULL) {
H A Dlpddr4_if.h108 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
116 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
H A Dlpddr4_j721e.c74 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) argument
80 result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
94 *irqstatus = true;
96 *irqstatus = false;
H A Dlpddr4_j721e_sanity.h16 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
18 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
26 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) argument
32 } else if (irqstatus == NULL) {
148 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) argument
154 } else if (irqstatus == NULL) {
H A Dlpddr4_obj_if.h45 u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
53 u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
/u-boot/drivers/video/ti/
H A Dtilcdc.c100 u32 irqstatus; member in struct:tilcdc_regs
/u-boot/include/linux/mtd/
H A Domap_gpmc.h64 u32 irqstatus; /* 0x18 */ member in struct:gpmc
/u-boot/include/
H A Domap3_spi.h64 unsigned int irqstatus; /* 0x18 */ member in struct:mcspi

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