1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
4 * Rohit Choraria <rohitkc@ti.com>
5 *
6 * (C) Copyright 2013 Andreas Bie��mann <andreas@biessmann.org>
7 */
8#ifndef __ASM_OMAP_GPMC_H
9#define __ASM_OMAP_GPMC_H
10
11/* Maximum Number of Chip Selects */
12#define GPMC_CS_NUM	8
13
14#define GPMC_BUF_EMPTY	0
15#define GPMC_BUF_FULL	1
16#define GPMC_MAX_SECTORS	8
17
18enum omap_ecc {
19	/* 1-bit  ECC calculation by Software, Error detection by Software */
20	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
21	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
22	/* ECC layout compatible to legacy ROMCODE. */
23	OMAP_ECC_HAM1_CODE_HW,
24	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
25	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
26	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
27	OMAP_ECC_BCH4_CODE_HW,
28	/* 8-bit  ECC calculation by GPMC, Error detection by Software */
29	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
30	/* 8-bit  ECC calculation by GPMC, Error detection by ELM */
31	OMAP_ECC_BCH8_CODE_HW,
32	/* 16-bit  ECC calculation by GPMC, Error detection by ELM */
33	OMAP_ECC_BCH16_CODE_HW,
34};
35
36struct gpmc_cs {
37	u32 config1;		/* 0x00 */
38	u32 config2;		/* 0x04 */
39	u32 config3;		/* 0x08 */
40	u32 config4;		/* 0x0C */
41	u32 config5;		/* 0x10 */
42	u32 config6;		/* 0x14 */
43	u32 config7;		/* 0x18 */
44	u32 nand_cmd;		/* 0x1C */
45	u32 nand_adr;		/* 0x20 */
46	u32 nand_dat;		/* 0x24 */
47	u8 res[8];		/* blow up to 0x30 byte */
48};
49
50struct bch_res_0_3 {
51	u32 bch_result_x[4];
52};
53
54struct bch_res_4_6 {
55	u32 bch_result_x[3];
56};
57
58struct gpmc {
59	u8 res1[0x10];
60	u32 sysconfig;		/* 0x10 */
61	u8 res2[0x4];
62	u32 irqstatus;		/* 0x18 */
63	u32 irqenable;		/* 0x1C */
64	u8 res3[0x20];
65	u32 timeout_control;	/* 0x40 */
66	u8 res4[0xC];
67	u32 config;		/* 0x50 */
68	u32 status;		/* 0x54 */
69	u8 res5[0x8];		/* 0x58 */
70	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
71	u32 prefetch_config1;	/* 0x1E0 */
72	u32 prefetch_config2;	/* 0x1E4 */
73	u32 res6;		/* 0x1E8 */
74	u32 prefetch_control;	/* 0x1EC */
75	u32 prefetch_status;	/* 0x1F0 */
76	u32 ecc_config;		/* 0x1F4 */
77	u32 ecc_control;	/* 0x1F8 */
78	u32 ecc_size_config;	/* 0x1FC */
79	u32 ecc1_result;	/* 0x200 */
80	u32 ecc2_result;	/* 0x204 */
81	u32 ecc3_result;	/* 0x208 */
82	u32 ecc4_result;	/* 0x20C */
83	u32 ecc5_result;	/* 0x210 */
84	u32 ecc6_result;	/* 0x214 */
85	u32 ecc7_result;	/* 0x218 */
86	u32 ecc8_result;	/* 0x21C */
87	u32 ecc9_result;	/* 0x220 */
88	u8 res7[12];		/* 0x224 */
89	u32 testmomde_ctrl;	/* 0x230 */
90	u8 res8[12];		/* 0x234 */
91	struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
92	u8 res9[16 * 4];	/* 0x2C0 - 0x2FF */
93	struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
94};
95
96/* Used for board specific gpmc initialization */
97extern const struct gpmc *gpmc_cfg;
98extern char gpmc_cs0_flash;
99
100#endif /* __ASM_OMAP_GPMC_H */
101