/linux-master/drivers/net/ethernet/marvell/octeon_ep/ |
H A D | octep_tx.c | 16 static void octep_iq_reset_indices(struct octep_iq *iq) argument 18 iq->fill_cnt = 0; 19 iq->host_write_index = 0; 20 iq->octep_read_index = 0; 21 iq->flush_index = 0; 22 iq->pkts_processed = 0; 23 iq->pkt_in_done = 0; 29 * @iq: Octeon Tx queue data structure. 32 int octep_iq_process_completions(struct octep_iq *iq, u16 budget) argument 35 struct octep_device *oct = iq 103 octep_iq_free_pending(struct octep_iq *iq) argument 178 struct octep_iq *iq; local 262 octep_free_iq(struct octep_iq *iq) argument [all...] |
H A D | octep_main.c | 65 ioq_vector->iq = oct->iq[i]; 560 * @iq: Octeon Tx queue data structure. 563 static void octep_enable_ioq_irq(struct octep_iq *iq, struct octep_oq *oq) argument 567 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); 568 if (iq->pkts_processed) { 569 writel(iq->pkts_processed, iq->inst_cnt_reg); 570 iq 803 octep_iq_full_check(struct octep_iq *iq) argument 851 struct octep_iq *iq; local 1009 struct octep_iq *iq = oct->iq[q]; local [all...] |
H A D | octep_config.h | 60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) 62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) 232 struct octep_iq_config iq; member in struct:octep_config
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H A D | octep_main.h | 50 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 54 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 97 u32 (*update_iq_read_idx)(struct octep_iq *iq); 150 struct octep_iq *iq; member in struct:octep_ioq_vector 258 struct octep_iq *iq[OCTEP_MAX_IQ]; member in struct:octep_device 403 int octep_iq_process_completions(struct octep_iq *iq, u1 [all...] |
/linux-master/drivers/net/ethernet/marvell/octeon_ep_vf/ |
H A D | octep_vf_tx.c | 17 static void octep_vf_iq_reset_indices(struct octep_vf_iq *iq) argument 19 iq->fill_cnt = 0; 20 iq->host_write_index = 0; 21 iq->octep_vf_read_index = 0; 22 iq->flush_index = 0; 23 iq->pkts_processed = 0; 24 iq->pkt_in_done = 0; 30 * @iq: Octeon Tx queue data structure. 33 int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget) argument 36 struct octep_vf_device *oct = iq 102 octep_vf_iq_free_pending(struct octep_vf_iq *iq) argument 177 struct octep_vf_iq *iq; local 261 octep_vf_free_iq(struct octep_vf_iq *iq) argument [all...] |
H A D | octep_vf_config.h | 56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) 58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) 149 struct octep_vf_iq_config iq; member in struct:octep_vf_config
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H A D | octep_vf_main.c | 64 ioq_vector->iq = oct->iq[i]; 293 * @iq: Octeon Tx queue data structure. 296 static void octep_vf_enable_ioq_irq(struct octep_vf_iq *iq, struct octep_vf_oq *oq) argument 300 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); 301 if (iq->pkts_processed) { 302 writel(iq->pkts_processed, iq->inst_cnt_reg); 303 iq 561 octep_vf_iq_full_check(struct octep_vf_iq *iq) argument 605 struct octep_vf_iq *iq; local 790 struct octep_vf_iq *iq = oct->iq[q]; local [all...] |
H A D | octep_vf_main.h | 35 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 39 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 64 u32 (*update_iq_read_idx)(struct octep_vf_iq *iq); 126 struct octep_vf_iq *iq; member in struct:octep_vf_ioq_vector 247 struct octep_vf_iq *iq[OCTEP_VF_MAX_IQ]; member in struct:octep_vf_device 328 int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u1 [all...] |
H A D | octep_vf_cn9k.c | 146 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; 147 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; 148 conf->iq.db_min = OCTEP_VF_DB_MIN; 149 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; 163 struct octep_vf_iq *iq = oct->iq[iq_no]; local 181 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); 182 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); 185 iq->doorbell_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_INSTR_DBELL(iq_no); 186 iq 352 octep_vf_update_iq_read_index_cn93(struct octep_vf_iq *iq) argument [all...] |
H A D | octep_vf_cnxk.c | 148 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; 149 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; 150 conf->iq.db_min = OCTEP_VF_DB_MIN; 151 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; 166 struct octep_vf_iq *iq = oct->iq[iq_no]; local 184 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); 185 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); 188 iq->doorbell_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no); 189 iq 363 octep_vf_update_iq_read_index_cnxk(struct octep_vf_iq *iq) argument [all...] |
H A D | octep_vf_ethtool.c | 125 struct octep_vf_iq *iq = oct->iq[q]; local 128 tx_busy_errors += iq->stats.tx_busy; 145 struct octep_vf_iq *iq = oct->iq[q]; local 147 data[i++] = iq->stats.instr_posted; 148 data[i++] = iq->stats.instr_completed; 149 data[i++] = iq->stats.bytes_sent; 150 data[i++] = iq->stats.tx_busy;
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/linux-master/drivers/net/ethernet/cavium/liquidio/ |
H A D | cn68xx_regs.h | 32 #define CN68XX_SLI_IQ_PORT_PKIND(iq) \ 33 (CN68XX_SLI_IQ_PORT0_PKIND + ((iq) * CN6XXX_IQ_OFFSET))
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H A D | request_manager.c | 51 struct octeon_instr_queue *iq; local 73 iq = oct->instr_queue[iq_no]; 75 iq->oct_dev = oct; 77 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma); 78 if (!iq->base_addr) { 84 iq->max_count = num_descs; 89 iq->request_list = vzalloc_node(array_size(num_descs, sizeof(*iq->request_list)), 91 if (!iq 159 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; local 265 ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq) argument 279 struct octeon_instr_queue *iq; local 289 __copy_cmd_into_iq(struct octeon_instr_queue *iq, u8 *cmd) argument 301 __post_command2(struct octeon_instr_queue *iq, u8 *cmd) argument 354 __add_to_request_list(struct octeon_instr_queue *iq, int idx, void *buf, int reqtype) argument 363 lio_process_iq_request_list(struct octeon_device *oct, struct octeon_instr_queue *iq, u32 napi_budget) argument 441 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, u32 napi_budget) argument 495 struct octeon_instr_queue *iq; local 542 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; local 687 struct octeon_instr_queue *iq; local [all...] |
H A D | cn23xx_vf_regs.h | 70 #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \ 71 (CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET)) 73 #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \ 74 (CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET)) 76 #define CN23XX_VF_SLI_IQ_SIZE(iq) \ 77 (CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET)) 79 #define CN23XX_VF_SLI_IQ_DOORBELL(iq) \ 80 (CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET)) 82 #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \ 83 (CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSE [all...] |
H A D | cn66xx_regs.h | 143 #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \ 144 (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) 146 #define CN6XXX_SLI_IQ_SIZE(iq) \ 147 (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET)) 149 #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \ 150 (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) 152 #define CN6XXX_SLI_IQ_DOORBELL(iq) \ 153 (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET)) 155 #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \ 156 (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSE [all...] |
H A D | octeon_config.h | 121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) 123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) 124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) 128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) 129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val 410 struct octeon_iq_config iq; member in struct:octeon_config
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H A D | cn23xx_vf_device.c | 104 struct octeon_instr_queue *iq; local 116 iq = oct->instr_queue[q_no]; 118 if (iq) 119 inst_cnt_reg = iq->inst_cnt_reg; 214 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; local 219 iq->base_addr_dma); 220 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count); 225 iq->doorbell_reg = 227 iq->inst_cnt_reg = 230 iq_no, iq 524 cn23xx_update_read_index(struct octeon_instr_queue *iq) argument [all...] |
H A D | cn23xx_pf_regs.h | 170 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ 171 (CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET)) 173 #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \ 174 (CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET)) 176 #define CN23XX_SLI_IQ_SIZE(iq) \ 177 (CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET)) 179 #define CN23XX_SLI_IQ_DOORBELL(iq) \ 180 (CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET)) 182 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ 183 (CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSE [all...] |
H A D | cn66xx_device.c | 266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; local 272 iq->base_addr_dma); 273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); 278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); 279 iq->inst_cnt_reg = oct->mmio[0].hw_addr 282 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); 287 iq->reset_instr_cnt = readl(iq->inst_cnt_reg); 339 mask |= oct->io_qmask.iq; 449 lio_cn6xxx_update_read_index(struct octeon_instr_queue *iq) argument [all...] |
H A D | octeon_device.c | 41 .iq = { 150 .iq = { 316 .iq = { 419 .iq = { 656 if (oct->io_qmask.iq & BIT_ULL(i)) 1286 (oct->io_qmask.iq & BIT_ULL(q_no))) 1452 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq) argument 1465 if (iq) { 1466 spin_lock_bh(&iq->lock); 1467 writel(iq [all...] |
/linux-master/drivers/crypto/cavium/zip/ |
H A D | zip_device.c | 59 return ((zip_dev->iq[queue].sw_head - zip_dev->iq[queue].sw_tail) * 98 spin_lock(&zip_dev->iq[queue].lock); 109 zip_dbg("sw_head : %lx", zip_dev->iq[queue].sw_head); 110 zip_dbg("sw_tail : %lx", zip_dev->iq[queue].sw_tail); 117 memcpy((u8 *)zip_dev->iq[queue].sw_head, (u8 *)instr, 119 zip_dev->iq[queue].sw_head += 16; /* 16 64_bit words = 128B */ 122 ncb_ptr = zip_dev->iq[queue].sw_head; 125 ncb_ptr, zip_dev->iq[queue].sw_head - 16); 128 zip_dev->iq[queu [all...] |
H A D | zip_mem.c | 59 zip->iq[q].sw_head = (u64 *)__get_free_pages((GFP_KERNEL | GFP_DMA), 62 if (!zip->iq[q].sw_head) 65 memset(zip->iq[q].sw_head, 0, ZIP_CMD_QBUF_SIZE); 67 zip_dbg("cmd_qbuf_alloc[%d] Success : %p\n", q, zip->iq[q].sw_head); 78 zip_dbg("Freeing cmd_qbuf 0x%lx\n", zip->iq[q].sw_tail); 80 free_pages((u64)zip->iq[q].sw_tail, get_order(ZIP_CMD_QBUF_SIZE));
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H A D | zip_main.c | 172 memset(&zip->iq[q], 0x0, sizeof(struct zip_iq)); 174 spin_lock_init(&zip->iq[q].lock); 185 zip->iq[q].sw_tail = zip->iq[q].sw_head; 186 zip->iq[q].hw_tail = zip->iq[q].sw_head; 190 que_sbuf_addr.s.ptr = (__pa(zip->iq[q].sw_head) >> 203 zip->iq[q].sw_head, zip->iq[q].sw_tail, 204 zip->iq[ [all...] |
/linux-master/drivers/crypto/marvell/octeontx2/ |
H A D | otx2_cptlf.h | 131 struct otx2_cpt_inst_queue *iq; local 135 iq = &lfs->lf[i].iqueue; 136 if (iq->real_vaddr) 138 iq->size, 139 iq->real_vaddr, 140 iq->real_dma_addr); 141 iq->real_vaddr = NULL; 142 iq->vaddr = NULL; 149 struct otx2_cpt_inst_queue *iq; local 156 iq [all...] |
/linux-master/drivers/scsi/csiostor/ |
H A D | csio_isr.c | 203 * @iq: Ingress queue pointer. 212 csio_scsi_isr_handler(struct csio_q *iq) argument 214 struct csio_hw *hw = (struct csio_hw *)iq->owner; 223 if (unlikely(csio_wr_process_iq(hw, iq, csio_process_scsi_cmpl, 258 struct csio_q *iq = (struct csio_q *) dev_id; local 261 if (unlikely(!iq)) 264 hw = (struct csio_hw *)iq->owner; 271 csio_scsi_isr_handler(iq); 288 struct csio_q *iq = priv; local 290 csio_scsi_isr_handler(iq); [all...] |