Searched refs:ih_rb_wptr (Results 1 - 7 of 7) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega10_ih.c | 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
125 WREG32(ih_regs->ih_rb_wptr, 0);
242 WREG32(ih_regs->ih_rb_wptr, 0);
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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| H A D | navi10_ih.c | 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
180 WREG32(ih_regs->ih_rb_wptr, 0);
298 WREG32(ih_regs->ih_rb_wptr, 0);
427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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| H A D | vega20_ih.c | 64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
134 WREG32(ih_regs->ih_rb_wptr, 0);
251 WREG32(ih_regs->ih_rb_wptr, 0);
406 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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| H A D | amdgpu_ih.h | 40 uint32_t ih_rb_wptr; member in struct:amdgpu_ih_regs
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| H A D | ih_v6_0.c | 57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
154 WREG32(ih_regs->ih_rb_wptr, 0);
274 WREG32(ih_regs->ih_rb_wptr, 0);
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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| H A D | ih_v6_1.c | 57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
154 WREG32(ih_regs->ih_rb_wptr, 0);
274 WREG32(ih_regs->ih_rb_wptr, 0);
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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| H A D | ih_v7_0.c | 57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
154 WREG32(ih_regs->ih_rb_wptr, 0);
274 WREG32(ih_regs->ih_rb_wptr, 0);
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
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