/linux-master/drivers/gpu/drm/msm/disp/mdp5/ |
H A D | mdp5.xml.h | 276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } argument 278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } argument 298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } argument 300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } argument 330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } argument 332 REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) argument 334 REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) argument 371 REG_MDP5_CTL(uint32_t i0) argument 385 REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) argument 387 REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) argument 451 REG_MDP5_CTL_OP(uint32_t i0) argument 473 REG_MDP5_CTL_FLUSH(uint32_t i0) argument 504 REG_MDP5_CTL_START(uint32_t i0) argument 506 REG_MDP5_CTL_PACK_3D(uint32_t i0) argument 520 REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) argument 522 REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) argument 565 REG_MDP5_PIPE(enum mdp5_pipe i0) argument 567 REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) argument 582 REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) argument 584 REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) argument 586 REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) argument 588 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) argument 602 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) argument 616 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) argument 630 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) argument 644 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) argument 652 REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) argument 654 REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) argument 668 REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) argument 670 REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) argument 684 REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) argument 686 REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) argument 694 REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) argument 696 REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) argument 704 REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) argument 718 REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) argument 732 REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) argument 746 REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) argument 760 REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) argument 774 REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) argument 776 REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) argument 778 REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) argument 780 REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) argument 782 REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) argument 796 REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) argument 810 REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) argument 812 REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) argument 866 REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) argument 892 REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) argument 909 REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) argument 911 REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) argument 913 REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) argument 915 REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) argument 917 REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) argument 919 REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) argument 921 REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) argument 923 REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) argument 925 REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) argument 927 REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) argument 929 REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) argument 931 REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) argument 954 REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) argument 956 REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) argument 982 REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) argument 1008 REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) argument 1022 REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) argument 1062 REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) argument 1064 REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) argument 1066 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) argument 1068 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) argument 1070 REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) argument 1072 REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) argument 1086 REG_MDP5_LM(uint32_t i0) argument 1088 REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) argument 1098 REG_MDP5_LM_OUT_SIZE(uint32_t i0) argument 1112 REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) argument 1114 REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) argument 1129 REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) argument 1131 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) argument 1153 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) argument 1155 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) argument 1157 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) argument 1159 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 1161 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 1163 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument 1165 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) argument 1167 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 1169 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 1171 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument 1173 REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) argument 1187 REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) argument 1201 REG_MDP5_LM_CURSOR_XY(uint32_t i0) argument 1215 REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) argument 1223 REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) argument 1231 REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) argument 1233 REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) argument 1247 REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) argument 1257 REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) argument 1259 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) argument 1261 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) argument 1263 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) argument 1265 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) argument 1267 REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) argument 1279 REG_MDP5_DSPP(uint32_t i0) argument 1281 REG_MDP5_DSPP_OP_MODE(uint32_t i0) argument 1298 REG_MDP5_DSPP_PCC_BASE(uint32_t i0) argument 1300 REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) argument 1302 REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) argument 1304 REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) argument 1306 REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) argument 1308 REG_MDP5_DSPP_PA_BASE(uint32_t i0) argument 1310 REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) argument 1312 REG_MDP5_DSPP_GC_BASE(uint32_t i0) argument 1324 REG_MDP5_PP(uint32_t i0) argument 1326 REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) argument 1328 REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) argument 1338 REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) argument 1340 REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) argument 1354 REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) argument 1356 REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) argument 1370 REG_MDP5_PP_SYNC_THRESH(uint32_t i0) argument 1384 REG_MDP5_PP_START_POS(uint32_t i0) argument 1386 REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) argument 1388 REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) argument 1390 REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) argument 1392 REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) argument 1394 REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) argument 1396 REG_MDP5_PP_FBC_MODE(uint32_t i0) argument 1398 REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) argument 1400 REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) argument 1415 REG_MDP5_WB(uint32_t i0) argument 1417 REG_MDP5_WB_DST_FORMAT(uint32_t i0) argument 1484 REG_MDP5_WB_DST_OP_MODE(uint32_t i0) argument 1538 REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) argument 1564 REG_MDP5_WB_DST0_ADDR(uint32_t i0) argument 1566 REG_MDP5_WB_DST1_ADDR(uint32_t i0) argument 1568 REG_MDP5_WB_DST2_ADDR(uint32_t i0) argument 1570 REG_MDP5_WB_DST3_ADDR(uint32_t i0) argument 1572 REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) argument 1586 REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) argument 1600 REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) argument 1602 REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) argument 1604 REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) argument 1606 REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) argument 1608 REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) argument 1610 REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) argument 1612 REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) argument 1614 REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) argument 1616 REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) argument 1618 REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) argument 1620 REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) argument 1622 REG_MDP5_WB_OUT_SIZE(uint32_t i0) argument 1636 REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) argument 1638 REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) argument 1652 REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) argument 1666 REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) argument 1680 REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) argument 1694 REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) argument 1702 REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) argument 1704 REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) argument 1718 REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) argument 1720 REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) argument 1734 REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) argument 1736 REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) argument 1744 REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) argument 1746 REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) argument 1765 REG_MDP5_INTF(uint32_t i0) argument 1767 REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) argument 1769 REG_MDP5_INTF_CONFIG(uint32_t i0) argument 1771 REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) argument 1785 REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) argument 1787 REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) argument 1789 REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) argument 1791 REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) argument 1793 REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) argument 1795 REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) argument 1797 REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) argument 1799 REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) argument 1801 REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) argument 1810 REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) argument 1818 REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) argument 1820 REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) argument 1822 REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) argument 1836 REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) argument 1851 REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) argument 1853 REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) argument 1855 REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) argument 1857 REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) argument 1862 REG_MDP5_INTF_TEST_CTL(uint32_t i0) argument 1864 REG_MDP5_INTF_TP_COLOR0(uint32_t i0) argument 1866 REG_MDP5_INTF_TP_COLOR1(uint32_t i0) argument 1868 REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) argument 1870 REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) argument 1872 REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) argument 1874 REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) argument 1876 REG_MDP5_INTF_LINE_COUNT(uint32_t i0) argument 1878 REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) argument 1880 REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) argument 1882 REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) argument 1884 REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) argument 1886 REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) argument 1888 REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) argument 1890 REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) argument 1892 REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) argument 1894 REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) argument 1896 REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) argument 1898 REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) argument 1908 REG_MDP5_AD(uint32_t i0) argument 1910 REG_MDP5_AD_BYPASS(uint32_t i0) argument 1912 REG_MDP5_AD_CTRL_0(uint32_t i0) argument 1914 REG_MDP5_AD_CTRL_1(uint32_t i0) argument 1916 REG_MDP5_AD_FRAME_SIZE(uint32_t i0) argument 1918 REG_MDP5_AD_CON_CTRL_0(uint32_t i0) argument 1920 REG_MDP5_AD_CON_CTRL_1(uint32_t i0) argument 1922 REG_MDP5_AD_STR_MAN(uint32_t i0) argument 1924 REG_MDP5_AD_VAR(uint32_t i0) argument 1926 REG_MDP5_AD_DITH(uint32_t i0) argument 1928 REG_MDP5_AD_DITH_CTRL(uint32_t i0) argument 1930 REG_MDP5_AD_AMP_LIM(uint32_t i0) argument 1932 REG_MDP5_AD_SLOPE(uint32_t i0) argument 1934 REG_MDP5_AD_BW_LVL(uint32_t i0) argument 1936 REG_MDP5_AD_LOGO_POS(uint32_t i0) argument 1938 REG_MDP5_AD_LUT_FI(uint32_t i0) argument 1940 REG_MDP5_AD_LUT_CC(uint32_t i0) argument 1942 REG_MDP5_AD_STR_LIM(uint32_t i0) argument 1944 REG_MDP5_AD_CALIB_AB(uint32_t i0) argument 1946 REG_MDP5_AD_CALIB_CD(uint32_t i0) argument 1948 REG_MDP5_AD_MODE_SEL(uint32_t i0) argument 1950 REG_MDP5_AD_TFILT_CTRL(uint32_t i0) argument 1952 REG_MDP5_AD_BL_MINMAX(uint32_t i0) argument 1954 REG_MDP5_AD_BL(uint32_t i0) argument 1956 REG_MDP5_AD_BL_MAX(uint32_t i0) argument 1958 REG_MDP5_AD_AL(uint32_t i0) argument 1960 REG_MDP5_AD_AL_MIN(uint32_t i0) argument 1962 REG_MDP5_AD_AL_FILT(uint32_t i0) argument 1964 REG_MDP5_AD_CFG_BUF(uint32_t i0) argument 1966 REG_MDP5_AD_LUT_AL(uint32_t i0) argument 1968 REG_MDP5_AD_TARG_STR(uint32_t i0) argument 1970 REG_MDP5_AD_START_CALC(uint32_t i0) argument 1972 REG_MDP5_AD_STR_OUT(uint32_t i0) argument 1974 REG_MDP5_AD_BL_OUT(uint32_t i0) argument 1976 REG_MDP5_AD_CALC_DONE(uint32_t i0) argument [all...] |
/linux-master/drivers/gpu/drm/msm/dsi/ |
H A D | dsi_phy_10nm.xml.h | 126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } argument 132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } argument 134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } argument 136 REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) argument 138 REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) argument 140 REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) argument 142 REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) argument 144 REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) argument 146 REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) argument 148 REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) argument 150 REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) argument [all...] |
H A D | dsi_phy_14nm.xml.h | 117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } argument 130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } argument 132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } argument 134 REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) argument 136 REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) argument 138 REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) argument 146 REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) argument 154 REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) argument 162 REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) argument 170 REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) argument 178 REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) argument 192 REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) argument 200 REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) argument 208 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) argument 210 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) argument 212 REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) argument [all...] |
H A D | mmss_cc.xml.h | 71 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } argument 73 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } argument 90 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } argument 104 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } argument
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H A D | dsi_phy_20nm.xml.h | 56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } argument 62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } argument 64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } argument 66 REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) argument 68 REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) argument 70 REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) argument 72 REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) argument 74 REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) argument [all...] |
H A D | dsi_phy_28nm_8960.xml.h | 56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } argument 62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } argument 64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } argument 66 REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) argument 68 REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) argument [all...] |
H A D | dsi_phy_28nm.xml.h | 56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } argument 60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } argument 62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } argument 64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } argument 66 REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) argument 68 REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) argument 70 REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) argument 72 REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) argument 74 REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) argument [all...] |
H A D | dsi_phy_7nm.xml.h | 160 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 162 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } argument 164 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } argument 166 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } argument 168 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } argument 170 REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) argument 172 REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) argument 174 REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) argument [all...] |
/linux-master/drivers/gpu/drm/msm/disp/mdp4/ |
H A D | mdp4.xml.h | 326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } argument 328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } argument 330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } argument 344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } argument 346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } argument 348 REG_MDP4_OVLP_OPMODE(uint32_t i0) argument 360 REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) argument 362 REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) argument 382 REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) argument 384 REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) argument 386 REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) argument 388 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 390 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 392 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument 404 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) argument 406 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) argument 409 REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) argument 411 REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) argument 413 REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) argument 415 REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) argument 417 REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) argument 419 REG_MDP4_OVLP_CSC(uint32_t i0) argument 422 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) argument 424 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) argument 426 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) argument 428 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) argument 430 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) argument 432 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) argument 434 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) argument 436 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) argument 438 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) argument 440 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) argument 444 REG_MDP4_LUTN(uint32_t i0) argument 446 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) argument 448 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) argument 452 REG_MDP4_DMA_E_QUANT(uint32_t i0) argument 463 REG_MDP4_DMA(enum mdp4_dma i0) argument 465 REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) argument 494 REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) argument 508 REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) argument 510 REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) argument 512 REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) argument 526 REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) argument 540 REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) argument 542 REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) argument 556 REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) argument 566 REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) argument 568 REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) argument 570 REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) argument 572 REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) argument 574 REG_MDP4_DMA_CSC(enum mdp4_dma i0) argument 577 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) argument 579 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) argument 581 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) argument 583 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) argument 585 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) argument 587 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) argument 589 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) argument 591 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) argument 593 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) argument 595 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) argument 597 REG_MDP4_PIPE(enum mdp4_pipe i0) argument 599 REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) argument 613 REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) argument 627 REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) argument 641 REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) argument 655 REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) argument 657 REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) argument 659 REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) argument 661 REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) argument 663 REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) argument 677 REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) argument 691 REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) argument 705 REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) argument 766 REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) argument 792 REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) argument 817 REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) argument 819 REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) argument 821 REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) argument 823 REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) argument 825 REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) argument 828 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) argument 830 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 832 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) argument 834 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 836 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) argument 838 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 840 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) argument 842 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 844 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) argument 846 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 945 REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) argument 947 REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) argument 973 REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) argument [all...] |
/linux-master/drivers/gpu/drm/etnaviv/ |
H A D | state.xml.h | 73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) 192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) 198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) [all...] |
/linux-master/arch/arm64/crypto/ |
H A D | aes-ce.S | 57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4 58 aes\de \i0\().16b, \k\().16b 59 aes\mc \i0\().16b, \i0\().16b 77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4 79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4 81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4 86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4 87 aes\de \i0\().16b, \k\().16b 98 eor \i0\() [all...] |
/linux-master/arch/sparc/lib/ |
H A D | divdi3.S | 14 cmp %i0,0 21 sub %g0,%i0,%o0 23 mov %o4,%i0 42 cmp %o4,%i0 46 subcc %i0,%o4,%g0 49 sub %i0,%o4,%i0 ! this kills msb of n 50 addx %i0,%i0,%i0 ! s [all...] |
H A D | udivdi3.S | 17 cmp %o3,%i0 22 subcc %i0,%o3,%g0 25 sub %i0,%o3,%i0 ! this kills msb of n 26 addx %i0,%i0,%i0 ! so this cannot give carry 29 subcc %i0,%o3,%g0 33 sub %i0,%o3,%i0 ! thi [all...] |
H A D | NGpage.S | 33 stxa %o2, [%i0 + 0x00] %asi 34 stxa %o3, [%i0 + 0x08] %asi 35 stxa %o4, [%i0 + 0x10] %asi 36 stxa %o5, [%i0 + 0x18] %asi 37 stxa %l2, [%i0 + 0x20] %asi 38 stxa %l3, [%i0 + 0x28] %asi 39 stxa %l4, [%i0 + 0x30] %asi 40 stxa %l5, [%i0 + 0x38] %asi 45 stxa %o2, [%i0 + 0x40] %asi 46 stxa %o3, [%i0 [all...] |
H A D | xor.S | 262 sub %i0, 64, %i0 305 subcc %i0, 64, %i0 364 srlx %i0, 6, %g1 365 mov %i1, %i0 372 ldda [%i0 + 0x00] %asi, %o0 /* %o0/%o1 = dest + 0x00 */ 373 ldda [%i0 + 0x10] %asi, %o2 /* %o2/%o3 = dest + 0x10 */ 374 ldda [%i0 + 0x20] %asi, %o4 /* %o4/%o5 = dest + 0x20 */ 375 ldda [%i0 [all...] |
H A D | memcpy.S | 298 andcc %i0, 3, %g0 300 andcc %i0, 1, %g0 302 andcc %i0, 2, %g0 306 stb %g5, [%i0] 309 add %i0, 1, %i0 313 stb %g3, [%i0] 316 add %i0, 2, %i0 317 stb %g3, [%i0 [all...] |
H A D | muldi3.S | 58 mov %i0, %o0 62 mov %l2, %i0 63 add %l2, %l0, %i0
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H A D | NGmemcpy.S | 87 add %i2, %i5, %i0 91 add %i2, %g1, %i0 96 add %i2, %g1, %i0 101 add %i2, %g1, %i0 106 add %i2, %g1, %i0 111 add %i2, %g1, %i0 116 add %i2, %g1, %i0 121 add %i2, %g1, %i0 126 add %i2, %g1, %i0 130 add %i2, %i4, %i0 [all...] |
/linux-master/fs/jffs2/ |
H A D | compr_rubin.c | 105 long i0, i1; local 119 i0 = A * rs->p / (A + B); 120 if (i0 <= 0) 121 i0 = 1; 123 if (i0 >= rs->p) 124 i0 = rs->p - 1; 126 i1 = rs->p - i0; 129 rs->p = i0; 132 rs->q += i0; 203 long i0, threshol local [all...] |
/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a4xx.xml.h | 980 #define REG_A4XX_RB_MRT(i0) (0x000020a4 + 0x5*(i0)) 982 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } argument 1000 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } argument 1034 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } argument 1036 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } argument 1044 REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) argument 1558 REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) argument 1560 REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) argument 1568 REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) argument 1572 REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) argument 1576 REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) argument 1580 REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) argument 2032 REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) argument 2036 REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) argument 2040 REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) argument 2044 REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) argument 2048 REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) argument 2052 REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) argument 2056 REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) argument 2060 REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) argument 2076 REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) argument 2216 REG_A4XX_CP_PROTECT_REG(uint32_t i0) argument 2268 REG_A4XX_CP_SCRATCH_REG(uint32_t i0) argument 2378 REG_A4XX_SP_VS_OUT_REG(uint32_t i0) argument 2406 REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) argument 2546 REG_A4XX_SP_FS_MRT_REG(uint32_t i0) argument 2650 REG_A4XX_SP_DS_OUT_REG(uint32_t i0) argument 2678 REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) argument 2748 REG_A4XX_SP_GS_OUT_REG(uint32_t i0) argument 2776 REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) argument 2876 REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) argument 2880 REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) argument 2908 REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) argument 2936 REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) argument 2940 REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) argument 3044 REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) argument 3060 REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) argument 3062 REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) argument 3070 REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) argument 3080 REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) argument [all...] |
H A D | a6xx.xml.h | 1433 #define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0)) 1435 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } argument 1437 #define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0)) 1439 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } argument 1466 #define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0)) 2644 REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) argument 2684 REG_A6XX_VSC_STATE_REG(uint32_t i0) argument 2688 REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) argument 2692 REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) argument 2798 REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) argument 2806 REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) argument 2814 REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) argument 2822 REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) argument 2830 REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) argument 2838 REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) argument 2848 REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) argument 2856 REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) argument 3198 REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) argument 3212 REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) argument 3228 REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) argument 3242 REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) argument 3975 REG_A6XX_RB_MRT_CONTROL(uint32_t i0) argument 3992 REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) argument 4030 REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) argument 4051 REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) argument 4073 REG_A6XX_RB_MRT_PITCH(uint32_t i0) argument 4082 REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) argument 4091 REG_A6XX_RB_MRT_BASE(uint32_t i0) argument 4093 REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) argument 4703 REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) argument 4705 REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) argument 5280 REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) argument 5284 REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) argument 5292 REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) argument 5337 REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) argument 5339 REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) argument 5341 REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) argument 5343 REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) argument 5345 REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) argument 6008 REG_A6XX_VFD_FETCH_BASE(uint32_t i0) argument 6010 REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) argument 6012 REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) argument 6016 REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) argument 6045 REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) argument 6049 REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) argument 6120 REG_A6XX_SP_VS_OUT_REG(uint32_t i0) argument 6148 REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) argument 6394 REG_A6XX_SP_DS_OUT_REG(uint32_t i0) argument 6422 REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) argument 6567 REG_A6XX_SP_GS_OUT_REG(uint32_t i0) argument 6595 REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) argument 6885 REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) argument 6896 REG_A6XX_SP_FS_MRT_REG(uint32_t i0) argument 6932 REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) argument 6975 REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) argument 7017 REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) argument 7234 REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument 7251 REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument 7370 REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument 7387 REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument 8614 REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument 8744 REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) argument [all...] |
H A D | a3xx.xml.h | 917 #define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0)) 919 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } argument 1224 #define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0)) 1226 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } argument 1249 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } argument 1277 REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) argument 1286 REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) argument 1894 REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) argument 1896 REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) argument 1906 REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) argument 1982 REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) argument 2010 REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) argument 2014 REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) argument 2101 REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) argument 2201 REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) argument 2409 REG_A3XX_SP_VS_OUT_REG(uint32_t i0) argument 2439 REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) argument 2685 REG_A3XX_SP_FS_MRT_REG(uint32_t i0) argument 2698 REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) argument 2854 REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) argument 2880 REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) argument 2882 REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) argument 2909 REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) argument 2911 REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) argument 2913 REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) argument 2915 REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) argument [all...] |
H A D | a5xx.xml.h | 1041 #define REG_A5XX_CP_SCRATCH(i0) (0x00000b78 + 0x1*(i0)) 1043 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } argument 1045 #define REG_A5XX_CP_PROTECT(i0) (0x00000880 + 0x1*(i0)) 1047 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } argument 1977 #define REG_A5XX_VSC_PIPE_CONFIG(i0) (0x00000bd0 + 0x1*(i0)) 1979 REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) argument 2007 REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) argument 2009 REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) argument 2013 REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) argument 3102 REG_A5XX_RB_MRT_CONTROL(uint32_t i0) argument 3119 REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) argument 3157 REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) argument 3184 REG_A5XX_RB_MRT_PITCH(uint32_t i0) argument 3193 REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) argument 3202 REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) argument 3204 REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) argument 3619 REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) argument 3621 REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) argument 3623 REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) argument 3632 REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) argument 3678 REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) argument 3682 REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) argument 3690 REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) argument 3775 REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) argument 3777 REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) argument 3779 REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) argument 3781 REG_A5XX_VPC_SO_NCOMP(uint32_t i0) argument 3783 REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) argument 3785 REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) argument 3787 REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) argument 3934 REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) argument 3936 REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) argument 3938 REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) argument 3940 REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) argument 3944 REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) argument 3967 REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) argument 3971 REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) argument 4122 REG_A5XX_SP_VS_OUT_REG(uint32_t i0) argument 4150 REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) argument 4315 REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) argument 4326 REG_A5XX_SP_FS_MRT_REG(uint32_t i0) argument [all...] |
/linux-master/arch/sparc/prom/ |
H A D | cif.S | 23 mov %i0, %o0 ! prom_args 42 mov %i0, %o0
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/linux-master/arch/sparc/kernel/ |
H A D | syscalls.S | 160 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0 173 srl %i0, 0, %o0 190 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0 203 mov %i0, %o0 219 srl %i0, 0, %o0 ! IEU0 230 mov %i0, %l5 ! IEU1 243 mov %i0, %o0 ! IEU0 254 mov %i0, %l5 ! IEU0
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