1#ifndef STATE_XML 2#define STATE_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://0x04.net/cgit/index.cgi/rules-ng-ng 8git clone git://0x04.net/rules-ng-ng 9 10The rules-ng-ng source files this header was generated from are: 11- state.xml ( 26087 bytes, from 2017-12-18 16:51:59) 12- common.xml ( 35468 bytes, from 2018-01-22 13:48:54) 13- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) 14- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) 15- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 16- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) 17- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) 18- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) 19- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) 20 21Copyright (C) 2012-2017 by the following authors: 22- Wladimir J. van der Laan <laanwj@gmail.com> 23- Christian Gmeiner <christian.gmeiner@gmail.com> 24- Lucas Stach <l.stach@pengutronix.de> 25- Russell King <rmk@arm.linux.org.uk> 26 27Permission is hereby granted, free of charge, to any person obtaining a 28copy of this software and associated documentation files (the "Software"), 29to deal in the Software without restriction, including without limitation 30the rights to use, copy, modify, merge, publish, distribute, sub license, 31and/or sell copies of the Software, and to permit persons to whom the 32Software is furnished to do so, subject to the following conditions: 33 34The above copyright notice and this permission notice (including the 35next paragraph) shall be included in all copies or substantial portions 36of the Software. 37 38THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44DEALINGS IN THE SOFTWARE. 45*/ 46 47 48#define VARYING_COMPONENT_USE_UNUSED 0x00000000 49#define VARYING_COMPONENT_USE_USED 0x00000001 50#define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 51#define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 52#define FE_DATA_TYPE_BYTE 0x00000000 53#define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001 54#define FE_DATA_TYPE_SHORT 0x00000002 55#define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 56#define FE_DATA_TYPE_INT 0x00000004 57#define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 58#define FE_DATA_TYPE_FLOAT 0x00000008 59#define FE_DATA_TYPE_HALF_FLOAT 0x00000009 60#define FE_DATA_TYPE_FIXED 0x0000000b 61#define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c 62#define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d 63#define FE_DATA_TYPE_BYTE_I 0x0000000e 64#define FE_DATA_TYPE_SHORT_I 0x0000000f 65#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff 66#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 67#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) 68#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000 69#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16 70#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK) 71#define VIVS_FE 0x00000000 72 73#define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) 74#define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004 75#define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 76#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f 77#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 78#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK) 79#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 80#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 81#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) 82#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080 83#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700 84#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 8 85#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK) 86#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000 87#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 12 88#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK) 89#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000 90#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14 91#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000 92#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000 93#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000 94#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16 95#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK) 96#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000 97#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24 98#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK) 99 100#define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640 101 102#define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644 103 104#define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648 105#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003 106#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0 107#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 108#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 109#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 110#define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100 111 112#define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c 113 114#define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650 115 116#define VIVS_FE_COMMAND_ADDRESS 0x00000654 117 118#define VIVS_FE_COMMAND_CONTROL 0x00000658 119#define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff 120#define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0 121#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK) 122#define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000 123 124#define VIVS_FE_DMA_STATUS 0x0000065c 125 126#define VIVS_FE_DMA_DEBUG_STATE 0x00000660 127#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f 128#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0 129#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000 130#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001 131#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002 132#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003 133#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004 134#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005 135#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006 136#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007 137#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008 138#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009 139#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a 140#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b 141#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c 142#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d 143#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e 144#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f 145#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010 146#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011 147#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012 148#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013 149#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014 150#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015 151#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300 152#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8 153#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000 154#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100 155#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200 156#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300 157#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00 158#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10 159#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000 160#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400 161#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800 162#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000 163#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12 164#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000 165#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000 166#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000 167#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000 168#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14 169#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000 170#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000 171#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000 172#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000 173#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16 174#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000 175#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000 176#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000 177 178#define VIVS_FE_DMA_ADDRESS 0x00000664 179 180#define VIVS_FE_DMA_LOW 0x00000668 181 182#define VIVS_FE_DMA_HIGH 0x0000066c 183 184#define VIVS_FE_AUTO_FLUSH 0x00000670 185 186#define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674 187 188#define VIVS_FE_UNK00678 0x00000678 189 190#define VIVS_FE_UNK0067C 0x0000067c 191 192#define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 193#define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004 194#define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008 195 196#define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) 197 198#define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 199 200#define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 201#define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004 202#define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010 203 204#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) 205 206#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) 207 208#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) 209 210#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) 211 212#define VIVS_FE_HALTI5_UNK007C4 0x000007c4 213 214#define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) 215#define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 216#define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002 217 218#define VIVS_FE_HALTI5_UNK007D8 0x000007d8 219 220#define VIVS_FE_DESC_START 0x000007dc 221 222#define VIVS_FE_DESC_END 0x000007e0 223 224#define VIVS_FE_DESC_AVAIL 0x000007e4 225#define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f 226#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0 227#define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK) 228 229#define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8 230 231#define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4 232 233#define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 234 235#define VIVS_GL 0x00000000 236 237#define VIVS_GL_PIPE_SELECT 0x00003800 238#define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001 239#define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0 240#define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK) 241 242#define VIVS_GL_EVENT 0x00003804 243#define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f 244#define VIVS_GL_EVENT_EVENT_ID__SHIFT 0 245#define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) 246#define VIVS_GL_EVENT_FROM_FE 0x00000020 247#define VIVS_GL_EVENT_FROM_PE 0x00000040 248#define VIVS_GL_EVENT_FROM_BLT 0x00000080 249#define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 250#define VIVS_GL_EVENT_SOURCE__SHIFT 8 251#define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) 252 253#define VIVS_GL_SEMAPHORE_TOKEN 0x00003808 254#define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f 255#define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0 256#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK) 257#define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 258#define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 259#define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) 260#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000 261#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28 262#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK) 263 264#define VIVS_GL_FLUSH_CACHE 0x0000380c 265#define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 266#define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002 267#define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004 268#define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008 269#define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 270#define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 271#define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 272#define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400 273#define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 274#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 275#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 276 277#define VIVS_GL_FLUSH_MMU 0x00003810 278#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 279#define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002 280#define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004 281#define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008 282#define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010 283 284#define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814 285 286#define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818 287#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003 288#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0 289#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000 290#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001 291#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002 292#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008 293#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0 294#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4 295#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK) 296#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100 297#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000 298#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12 299#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK) 300#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000 301#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000 302#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16 303#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK) 304#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000 305 306#define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c 307#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff 308#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0 309#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) 310 311#define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 312 313#define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824 314 315#define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) 316#define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 317#define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002 318#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003 319#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0 320#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK) 321#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c 322#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2 323#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK) 324#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030 325#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4 326#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK) 327#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0 328#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6 329#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK) 330#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300 331#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8 332#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK) 333#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00 334#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10 335#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK) 336#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000 337#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12 338#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK) 339#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000 340#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14 341#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK) 342#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000 343#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16 344#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK) 345#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000 346#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18 347#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK) 348#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000 349#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20 350#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK) 351#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000 352#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22 353#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK) 354#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000 355#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24 356#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK) 357#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000 358#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26 359#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK) 360#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000 361#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28 362#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK) 363#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000 364#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 365#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) 366 367#define VIVS_GL_UNK0382C 0x0000382c 368 369#define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 370 371#define VIVS_GL_UNK03834 0x00003834 372 373#define VIVS_GL_UNK03838 0x00003838 374 375#define VIVS_GL_API_MODE 0x0000384c 376#define VIVS_GL_API_MODE_OPENGL 0x00000000 377#define VIVS_GL_API_MODE_OPENVG 0x00000001 378#define VIVS_GL_API_MODE_OPENCL 0x00000002 379 380#define VIVS_GL_CONTEXT_POINTER 0x00003850 381 382#define VIVS_GL_UNK03854 0x00003854 383 384#define VIVS_GL_BUG_FIXES 0x00003860 385 386#define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868 387 388#define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c 389 390#define VIVS_GL_HALTI5_UNK03884 0x00003884 391 392#define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 393#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f 394#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0 395#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK) 396#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00 397#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8 398#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK) 399#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000 400#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16 401#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK) 402#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000 403#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24 404#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK) 405 406#define VIVS_GL_GS_UNK0388C 0x0000388c 407 408#define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898 409 410#define VIVS_GL_SHADER_INDEX 0x0000389c 411 412#define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) 413#define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004 414#define VIVS_GL_GS_UNK038A0__LEN 0x00000008 415 416#define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) 417#define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004 418#define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010 419 420#define VIVS_GL_SECURITY_UNK3900 0x00003900 421 422#define VIVS_GL_SECURITY_UNK3904 0x00003904 423 424#define VIVS_GL_UNK03A00 0x00003a00 425 426#define VIVS_GL_UNK03A04 0x00003a04 427 428#define VIVS_GL_UNK03A08 0x00003a08 429 430#define VIVS_GL_UNK03A0C 0x00003a0c 431 432#define VIVS_GL_UNK03A10 0x00003a10 433 434#define VIVS_GL_STALL_TOKEN 0x00003c00 435#define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f 436#define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0 437#define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK) 438#define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00 439#define VIVS_GL_STALL_TOKEN_TO__SHIFT 8 440#define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK) 441#define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 442#define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 443 444#define VIVS_NFE 0x00000000 445 446#define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 447#define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004 448#define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010 449 450#define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) 451 452#define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) 453 454#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) 455 456#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) 457 458#define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 459#define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004 460#define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020 461 462#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) 463#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f 464#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0 465#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK) 466#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030 467#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4 468#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK) 469#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700 470#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8 471#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK) 472#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000 473#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12 474#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK) 475#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000 476#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14 477#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000 478#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000 479#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000 480#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16 481#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK) 482 483#define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) 484 485#define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) 486 487#define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) 488 489#define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) 490 491#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) 492#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff 493#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0 494#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK) 495#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800 496 497#define VIVS_DUMMY 0x00000000 498 499#define VIVS_DUMMY_DUMMY 0x0003fffc 500 501 502#endif /* STATE_XML */ 503