1#ifndef MDP5_XML 2#define MDP5_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) 12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) 14- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) 15- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) 16- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) 17- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) 18- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) 19- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) 20- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) 21- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) 22- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) 23- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) 24- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) 25- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) 26- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) 27- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) 28- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) 29 30Copyright (C) 2013-2022 by the following authors: 31- Rob Clark <robdclark@gmail.com> (robclark) 32- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34Permission is hereby granted, free of charge, to any person obtaining 35a copy of this software and associated documentation files (the 36"Software"), to deal in the Software without restriction, including 37without limitation the rights to use, copy, modify, merge, publish, 38distribute, sublicense, and/or sell copies of the Software, and to 39permit persons to whom the Software is furnished to do so, subject to 40the following conditions: 41 42The above copyright notice and this permission notice (including the 43next paragraph) shall be included in all copies or substantial 44portions of the Software. 45 46THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53*/ 54 55 56enum mdp5_intf_type { 57 INTF_DISABLED = 0, 58 INTF_DSI = 1, 59 INTF_HDMI = 3, 60 INTF_LCDC = 5, 61 INTF_eDP = 9, 62 INTF_VIRTUAL = 100, 63 INTF_WB = 101, 64}; 65 66enum mdp5_intfnum { 67 NO_INTF = 0, 68 INTF0 = 1, 69 INTF1 = 2, 70 INTF2 = 3, 71 INTF3 = 4, 72}; 73 74enum mdp5_pipe { 75 SSPP_NONE = 0, 76 SSPP_VIG0 = 1, 77 SSPP_VIG1 = 2, 78 SSPP_VIG2 = 3, 79 SSPP_RGB0 = 4, 80 SSPP_RGB1 = 5, 81 SSPP_RGB2 = 6, 82 SSPP_DMA0 = 7, 83 SSPP_DMA1 = 8, 84 SSPP_VIG3 = 9, 85 SSPP_RGB3 = 10, 86 SSPP_CURSOR0 = 11, 87 SSPP_CURSOR1 = 12, 88}; 89 90enum mdp5_format { 91 DUMMY = 0, 92}; 93 94enum mdp5_ctl_mode { 95 MODE_NONE = 0, 96 MODE_WB_0_BLOCK = 1, 97 MODE_WB_1_BLOCK = 2, 98 MODE_WB_0_LINE = 3, 99 MODE_WB_1_LINE = 4, 100 MODE_WB_2_LINE = 5, 101}; 102 103enum mdp5_pack_3d { 104 PACK_3D_FRAME_INT = 0, 105 PACK_3D_H_ROW_INT = 1, 106 PACK_3D_V_ROW_INT = 2, 107 PACK_3D_COL_INT = 3, 108}; 109 110enum mdp5_scale_filter { 111 SCALE_FILTER_NEAREST = 0, 112 SCALE_FILTER_BIL = 1, 113 SCALE_FILTER_PCMN = 2, 114 SCALE_FILTER_CA = 3, 115}; 116 117enum mdp5_pipe_bwc { 118 BWC_LOSSLESS = 0, 119 BWC_Q_HIGH = 1, 120 BWC_Q_MED = 2, 121}; 122 123enum mdp5_cursor_format { 124 CURSOR_FMT_ARGB8888 = 0, 125 CURSOR_FMT_ARGB1555 = 2, 126 CURSOR_FMT_ARGB4444 = 4, 127}; 128 129enum mdp5_cursor_alpha { 130 CURSOR_ALPHA_CONST = 0, 131 CURSOR_ALPHA_PER_PIXEL = 2, 132}; 133 134enum mdp5_igc_type { 135 IGC_VIG = 0, 136 IGC_RGB = 1, 137 IGC_DMA = 2, 138 IGC_DSPP = 3, 139}; 140 141enum mdp5_data_format { 142 DATA_FORMAT_RGB = 0, 143 DATA_FORMAT_YUV = 1, 144}; 145 146enum mdp5_block_size { 147 BLOCK_SIZE_64 = 0, 148 BLOCK_SIZE_128 = 1, 149}; 150 151enum mdp5_rotate_mode { 152 ROTATE_0 = 0, 153 ROTATE_90 = 1, 154}; 155 156enum mdp5_chroma_downsample_method { 157 DS_MTHD_NO_PIXEL_DROP = 0, 158 DS_MTHD_PIXEL_DROP = 1, 159}; 160 161#define MDP5_IRQ_WB_0_DONE 0x00000001 162#define MDP5_IRQ_WB_1_DONE 0x00000002 163#define MDP5_IRQ_WB_2_DONE 0x00000010 164#define MDP5_IRQ_PING_PONG_0_DONE 0x00000100 165#define MDP5_IRQ_PING_PONG_1_DONE 0x00000200 166#define MDP5_IRQ_PING_PONG_2_DONE 0x00000400 167#define MDP5_IRQ_PING_PONG_3_DONE 0x00000800 168#define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000 169#define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000 170#define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000 171#define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000 172#define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000 173#define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000 174#define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000 175#define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000 176#define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000 177#define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000 178#define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000 179#define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000 180#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000 181#define MDP5_IRQ_INTF0_VSYNC 0x02000000 182#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000 183#define MDP5_IRQ_INTF1_VSYNC 0x08000000 184#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000 185#define MDP5_IRQ_INTF2_VSYNC 0x20000000 186#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000 187#define MDP5_IRQ_INTF3_VSYNC 0x80000000 188#define REG_MDSS_HW_VERSION 0x00000000 189#define MDSS_HW_VERSION_STEP__MASK 0x0000ffff 190#define MDSS_HW_VERSION_STEP__SHIFT 0 191static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) 192{ 193 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; 194} 195#define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000 196#define MDSS_HW_VERSION_MINOR__SHIFT 16 197static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) 198{ 199 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; 200} 201#define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000 202#define MDSS_HW_VERSION_MAJOR__SHIFT 28 203static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) 204{ 205 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; 206} 207 208#define REG_MDSS_HW_INTR_STATUS 0x00000010 209#define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001 210#define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010 211#define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020 212#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100 213#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000 214 215#define REG_MDP5_HW_VERSION 0x00000000 216#define MDP5_HW_VERSION_STEP__MASK 0x0000ffff 217#define MDP5_HW_VERSION_STEP__SHIFT 0 218static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) 219{ 220 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK; 221} 222#define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000 223#define MDP5_HW_VERSION_MINOR__SHIFT 16 224static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) 225{ 226 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK; 227} 228#define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000 229#define MDP5_HW_VERSION_MAJOR__SHIFT 28 230static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) 231{ 232 return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK; 233} 234 235#define REG_MDP5_DISP_INTF_SEL 0x00000004 236#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff 237#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0 238static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) 239{ 240 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK; 241} 242#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00 243#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8 244static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) 245{ 246 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK; 247} 248#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000 249#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16 250static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) 251{ 252 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK; 253} 254#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000 255#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24 256static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) 257{ 258 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK; 259} 260 261#define REG_MDP5_INTR_EN 0x00000010 262 263#define REG_MDP5_INTR_STATUS 0x00000014 264 265#define REG_MDP5_INTR_CLEAR 0x00000018 266 267#define REG_MDP5_HIST_INTR_EN 0x0000001c 268 269#define REG_MDP5_HIST_INTR_STATUS 0x00000020 270 271#define REG_MDP5_HIST_INTR_CLEAR 0x00000024 272 273#define REG_MDP5_SPARE_0 0x00000028 274#define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001 275 276static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } 277 278static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } 279#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff 280#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0 281static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) 282{ 283 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; 284} 285#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00 286#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8 287static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) 288{ 289 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; 290} 291#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000 292#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16 293static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) 294{ 295 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; 296} 297 298static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } 299 300static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } 301#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff 302#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0 303static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) 304{ 305 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK; 306} 307#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00 308#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8 309static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) 310{ 311 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK; 312} 313#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000 314#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16 315static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) 316{ 317 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK; 318} 319 320static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) 321{ 322 switch (idx) { 323 case IGC_VIG: return 0x00000200; 324 case IGC_RGB: return 0x00000210; 325 case IGC_DMA: return 0x00000220; 326 case IGC_DSPP: return 0x00000300; 327 default: return INVALID_IDX(idx); 328 } 329} 330static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } 331 332static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } 333 334static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } 335#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff 336#define MDP5_IGC_LUT_REG_VAL__SHIFT 0 337static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) 338{ 339 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK; 340} 341#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000 342#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000 343#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 344#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 345 346#define REG_MDP5_SPLIT_DPL_EN 0x000002f4 347 348#define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8 349#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 350#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 351#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 352#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 353 354#define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0 355#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 356#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 357#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 358#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 359 360static inline uint32_t __offset_CTL(uint32_t idx) 361{ 362 switch (idx) { 363 case 0: return (mdp5_cfg->ctl.base[0]); 364 case 1: return (mdp5_cfg->ctl.base[1]); 365 case 2: return (mdp5_cfg->ctl.base[2]); 366 case 3: return (mdp5_cfg->ctl.base[3]); 367 case 4: return (mdp5_cfg->ctl.base[4]); 368 default: return INVALID_IDX(idx); 369 } 370} 371static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } 372 373static inline uint32_t __offset_LAYER(uint32_t idx) 374{ 375 switch (idx) { 376 case 0: return 0x00000000; 377 case 1: return 0x00000004; 378 case 2: return 0x00000008; 379 case 3: return 0x0000000c; 380 case 4: return 0x00000010; 381 case 5: return 0x00000024; 382 default: return INVALID_IDX(idx); 383 } 384} 385static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } 386 387static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } 388#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007 389#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0 390static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val) 391{ 392 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK; 393} 394#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038 395#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3 396static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val) 397{ 398 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK; 399} 400#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0 401#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6 402static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val) 403{ 404 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK; 405} 406#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00 407#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9 408static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val) 409{ 410 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK; 411} 412#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000 413#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12 414static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val) 415{ 416 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK; 417} 418#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000 419#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15 420static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val) 421{ 422 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK; 423} 424#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000 425#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18 426static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val) 427{ 428 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK; 429} 430#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000 431#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21 432static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val) 433{ 434 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK; 435} 436#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000 437#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000 438#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000 439#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26 440static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val) 441{ 442 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK; 443} 444#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000 445#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29 446static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val) 447{ 448 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK; 449} 450 451static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } 452#define MDP5_CTL_OP_MODE__MASK 0x0000000f 453#define MDP5_CTL_OP_MODE__SHIFT 0 454static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) 455{ 456 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK; 457} 458#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070 459#define MDP5_CTL_OP_INTF_NUM__SHIFT 4 460static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) 461{ 462 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK; 463} 464#define MDP5_CTL_OP_CMD_MODE 0x00020000 465#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000 466#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000 467#define MDP5_CTL_OP_PACK_3D__SHIFT 20 468static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) 469{ 470 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK; 471} 472 473static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } 474#define MDP5_CTL_FLUSH_VIG0 0x00000001 475#define MDP5_CTL_FLUSH_VIG1 0x00000002 476#define MDP5_CTL_FLUSH_VIG2 0x00000004 477#define MDP5_CTL_FLUSH_RGB0 0x00000008 478#define MDP5_CTL_FLUSH_RGB1 0x00000010 479#define MDP5_CTL_FLUSH_RGB2 0x00000020 480#define MDP5_CTL_FLUSH_LM0 0x00000040 481#define MDP5_CTL_FLUSH_LM1 0x00000080 482#define MDP5_CTL_FLUSH_LM2 0x00000100 483#define MDP5_CTL_FLUSH_LM3 0x00000200 484#define MDP5_CTL_FLUSH_LM4 0x00000400 485#define MDP5_CTL_FLUSH_DMA0 0x00000800 486#define MDP5_CTL_FLUSH_DMA1 0x00001000 487#define MDP5_CTL_FLUSH_DSPP0 0x00002000 488#define MDP5_CTL_FLUSH_DSPP1 0x00004000 489#define MDP5_CTL_FLUSH_DSPP2 0x00008000 490#define MDP5_CTL_FLUSH_WB 0x00010000 491#define MDP5_CTL_FLUSH_CTL 0x00020000 492#define MDP5_CTL_FLUSH_VIG3 0x00040000 493#define MDP5_CTL_FLUSH_RGB3 0x00080000 494#define MDP5_CTL_FLUSH_LM5 0x00100000 495#define MDP5_CTL_FLUSH_DSPP3 0x00200000 496#define MDP5_CTL_FLUSH_CURSOR_0 0x00400000 497#define MDP5_CTL_FLUSH_CURSOR_1 0x00800000 498#define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000 499#define MDP5_CTL_FLUSH_TIMING_3 0x10000000 500#define MDP5_CTL_FLUSH_TIMING_2 0x20000000 501#define MDP5_CTL_FLUSH_TIMING_1 0x40000000 502#define MDP5_CTL_FLUSH_TIMING_0 0x80000000 503 504static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } 505 506static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } 507 508static inline uint32_t __offset_LAYER_EXT(uint32_t idx) 509{ 510 switch (idx) { 511 case 0: return 0x00000040; 512 case 1: return 0x00000044; 513 case 2: return 0x00000048; 514 case 3: return 0x0000004c; 515 case 4: return 0x00000050; 516 case 5: return 0x00000054; 517 default: return INVALID_IDX(idx); 518 } 519} 520static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } 521 522static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } 523#define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001 524#define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004 525#define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010 526#define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040 527#define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100 528#define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400 529#define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000 530#define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000 531#define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000 532#define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000 533#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000 534#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20 535static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val) 536{ 537 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK; 538} 539#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000 540#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26 541static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val) 542{ 543 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK; 544} 545 546static inline uint32_t __offset_PIPE(enum mdp5_pipe idx) 547{ 548 switch (idx) { 549 case SSPP_NONE: return (INVALID_IDX(idx)); 550 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]); 551 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); 552 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); 553 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]); 554 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]); 555 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]); 556 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); 557 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); 558 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]); 559 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]); 560 case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]); 561 case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]); 562 default: return INVALID_IDX(idx); 563 } 564} 565static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } 566 567static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); } 568#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000 569#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19 570static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val) 571{ 572 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK; 573} 574#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000 575#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18 576static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val) 577{ 578 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; 579} 580#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000 581 582static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); } 583 584static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); } 585 586static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); } 587 588static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); } 589#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff 590#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0 591static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val) 592{ 593 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK; 594} 595#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000 596#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16 597static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val) 598{ 599 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK; 600} 601 602static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); } 603#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff 604#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0 605static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val) 606{ 607 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK; 608} 609#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000 610#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16 611static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val) 612{ 613 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK; 614} 615 616static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); } 617#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff 618#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0 619static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val) 620{ 621 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK; 622} 623#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000 624#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16 625static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val) 626{ 627 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK; 628} 629 630static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); } 631#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff 632#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0 633static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val) 634{ 635 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK; 636} 637#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000 638#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16 639static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val) 640{ 641 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK; 642} 643 644static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); } 645#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff 646#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0 647static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val) 648{ 649 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK; 650} 651 652static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } 653 654static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } 655#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff 656#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0 657static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val) 658{ 659 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK; 660} 661#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00 662#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8 663static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val) 664{ 665 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK; 666} 667 668static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } 669 670static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } 671#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff 672#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0 673static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val) 674{ 675 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK; 676} 677#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00 678#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8 679static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val) 680{ 681 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK; 682} 683 684static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } 685 686static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } 687#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff 688#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0 689static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val) 690{ 691 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK; 692} 693 694static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } 695 696static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } 697#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff 698#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0 699static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val) 700{ 701 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK; 702} 703 704static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } 705#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 706#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 707static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) 708{ 709 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK; 710} 711#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff 712#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0 713static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) 714{ 715 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK; 716} 717 718static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); } 719#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000 720#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16 721static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) 722{ 723 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK; 724} 725#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff 726#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0 727static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) 728{ 729 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK; 730} 731 732static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); } 733#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000 734#define MDP5_PIPE_SRC_XY_Y__SHIFT 16 735static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) 736{ 737 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK; 738} 739#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff 740#define MDP5_PIPE_SRC_XY_X__SHIFT 0 741static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) 742{ 743 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK; 744} 745 746static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); } 747#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000 748#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16 749static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) 750{ 751 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK; 752} 753#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff 754#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0 755static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) 756{ 757 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK; 758} 759 760static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); } 761#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000 762#define MDP5_PIPE_OUT_XY_Y__SHIFT 16 763static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) 764{ 765 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK; 766} 767#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff 768#define MDP5_PIPE_OUT_XY_X__SHIFT 0 769static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) 770{ 771 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK; 772} 773 774static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); } 775 776static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); } 777 778static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); } 779 780static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); } 781 782static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); } 783#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 784#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0 785static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) 786{ 787 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK; 788} 789#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 790#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16 791static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) 792{ 793 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK; 794} 795 796static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); } 797#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 798#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0 799static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) 800{ 801 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK; 802} 803#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 804#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16 805static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) 806{ 807 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK; 808} 809 810static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); } 811 812static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); } 813#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 814#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 815static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) 816{ 817 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK; 818} 819#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 820#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 821static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) 822{ 823 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK; 824} 825#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 826#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 827static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) 828{ 829 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK; 830} 831#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 832#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 833static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) 834{ 835 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK; 836} 837#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 838#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 839#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9 840static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) 841{ 842 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK; 843} 844#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800 845#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000 846#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12 847static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) 848{ 849 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; 850} 851#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 852#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 853#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000 854#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19 855static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val) 856{ 857 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK; 858} 859#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000 860#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23 861static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) 862{ 863 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; 864} 865 866static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); } 867#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 868#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 869static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) 870{ 871 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK; 872} 873#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 874#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 875static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) 876{ 877 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK; 878} 879#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 880#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 881static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) 882{ 883 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK; 884} 885#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 886#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 887static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) 888{ 889 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK; 890} 891 892static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); } 893#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001 894#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006 895#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1 896static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) 897{ 898 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK; 899} 900#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000 901#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000 902#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000 903#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000 904#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000 905#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000 906#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000 907#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000 908 909static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } 910 911static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); } 912 913static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); } 914 915static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); } 916 917static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); } 918 919static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); } 920 921static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); } 922 923static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); } 924 925static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); } 926 927static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); } 928 929static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); } 930 931static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); } 932#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff 933#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0 934static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) 935{ 936 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK; 937} 938#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00 939#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8 940static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) 941{ 942 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; 943} 944 945static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx) 946{ 947 switch (idx) { 948 case COMP_0: return 0x00000100; 949 case COMP_1_2: return 0x00000110; 950 case COMP_3: return 0x00000120; 951 default: return INVALID_IDX(idx); 952 } 953} 954static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } 955 956static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } 957#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff 958#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0 959static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val) 960{ 961 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK; 962} 963#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00 964#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8 965static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val) 966{ 967 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK; 968} 969#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000 970#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16 971static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val) 972{ 973 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK; 974} 975#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000 976#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24 977static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val) 978{ 979 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK; 980} 981 982static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } 983#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff 984#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0 985static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val) 986{ 987 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK; 988} 989#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00 990#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8 991static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val) 992{ 993 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK; 994} 995#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000 996#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16 997static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val) 998{ 999 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK; 1000} 1001#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000 1002#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24 1003static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val) 1004{ 1005 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK; 1006} 1007 1008static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } 1009#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff 1010#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0 1011static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val) 1012{ 1013 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK; 1014} 1015#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000 1016#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16 1017static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val) 1018{ 1019 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK; 1020} 1021 1022static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } 1023#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001 1024#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002 1025#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300 1026#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8 1027static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val) 1028{ 1029 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK; 1030} 1031#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00 1032#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10 1033static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val) 1034{ 1035 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK; 1036} 1037#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000 1038#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12 1039static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val) 1040{ 1041 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK; 1042} 1043#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000 1044#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14 1045static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val) 1046{ 1047 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK; 1048} 1049#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000 1050#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16 1051static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val) 1052{ 1053 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK; 1054} 1055#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000 1056#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18 1057static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val) 1058{ 1059 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK; 1060} 1061 1062static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); } 1063 1064static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); } 1065 1066static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); } 1067 1068static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); } 1069 1070static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); } 1071 1072static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); } 1073 1074static inline uint32_t __offset_LM(uint32_t idx) 1075{ 1076 switch (idx) { 1077 case 0: return (mdp5_cfg->lm.base[0]); 1078 case 1: return (mdp5_cfg->lm.base[1]); 1079 case 2: return (mdp5_cfg->lm.base[2]); 1080 case 3: return (mdp5_cfg->lm.base[3]); 1081 case 4: return (mdp5_cfg->lm.base[4]); 1082 case 5: return (mdp5_cfg->lm.base[5]); 1083 default: return INVALID_IDX(idx); 1084 } 1085} 1086static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } 1087 1088static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } 1089#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002 1090#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004 1091#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008 1092#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010 1093#define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA 0x00000020 1094#define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA 0x00000040 1095#define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA 0x00000080 1096#define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT 0x80000000 1097 1098static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } 1099#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000 1100#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16 1101static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) 1102{ 1103 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK; 1104} 1105#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff 1106#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0 1107static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) 1108{ 1109 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK; 1110} 1111 1112static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); } 1113 1114static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); } 1115 1116static inline uint32_t __offset_BLEND(uint32_t idx) 1117{ 1118 switch (idx) { 1119 case 0: return 0x00000020; 1120 case 1: return 0x00000050; 1121 case 2: return 0x00000080; 1122 case 3: return 0x000000b0; 1123 case 4: return 0x00000230; 1124 case 5: return 0x00000260; 1125 case 6: return 0x00000290; 1126 default: return INVALID_IDX(idx); 1127 } 1128} 1129static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } 1130 1131static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } 1132#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003 1133#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0 1134static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) 1135{ 1136 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK; 1137} 1138#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004 1139#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008 1140#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010 1141#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020 1142#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300 1143#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8 1144static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) 1145{ 1146 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK; 1147} 1148#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400 1149#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800 1150#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000 1151#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000 1152 1153static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } 1154 1155static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } 1156 1157static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } 1158 1159static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } 1160 1161static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } 1162 1163static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } 1164 1165static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } 1166 1167static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } 1168 1169static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } 1170 1171static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } 1172 1173static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); } 1174#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff 1175#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0 1176static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val) 1177{ 1178 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK; 1179} 1180#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000 1181#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16 1182static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val) 1183{ 1184 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK; 1185} 1186 1187static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } 1188#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff 1189#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0 1190static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val) 1191{ 1192 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK; 1193} 1194#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000 1195#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16 1196static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val) 1197{ 1198 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK; 1199} 1200 1201static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } 1202#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff 1203#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0 1204static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val) 1205{ 1206 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK; 1207} 1208#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000 1209#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16 1210static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val) 1211{ 1212 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK; 1213} 1214 1215static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); } 1216#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff 1217#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0 1218static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val) 1219{ 1220 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK; 1221} 1222 1223static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); } 1224#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007 1225#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0 1226static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val) 1227{ 1228 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK; 1229} 1230 1231static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); } 1232 1233static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); } 1234#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff 1235#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0 1236static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val) 1237{ 1238 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK; 1239} 1240#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000 1241#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16 1242static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val) 1243{ 1244 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK; 1245} 1246 1247static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); } 1248#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001 1249#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006 1250#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1 1251static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val) 1252{ 1253 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK; 1254} 1255#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008 1256 1257static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); } 1258 1259static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); } 1260 1261static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); } 1262 1263static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); } 1264 1265static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); } 1266 1267static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } 1268 1269static inline uint32_t __offset_DSPP(uint32_t idx) 1270{ 1271 switch (idx) { 1272 case 0: return (mdp5_cfg->dspp.base[0]); 1273 case 1: return (mdp5_cfg->dspp.base[1]); 1274 case 2: return (mdp5_cfg->dspp.base[2]); 1275 case 3: return (mdp5_cfg->dspp.base[3]); 1276 default: return INVALID_IDX(idx); 1277 } 1278} 1279static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } 1280 1281static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } 1282#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001 1283#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e 1284#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1 1285static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) 1286{ 1287 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK; 1288} 1289#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010 1290#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100 1291#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000 1292#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000 1293#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000 1294#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000 1295#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000 1296#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000 1297 1298static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); } 1299 1300static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); } 1301 1302static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); } 1303 1304static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); } 1305 1306static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); } 1307 1308static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } 1309 1310static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); } 1311 1312static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } 1313 1314static inline uint32_t __offset_PP(uint32_t idx) 1315{ 1316 switch (idx) { 1317 case 0: return (mdp5_cfg->pp.base[0]); 1318 case 1: return (mdp5_cfg->pp.base[1]); 1319 case 2: return (mdp5_cfg->pp.base[2]); 1320 case 3: return (mdp5_cfg->pp.base[3]); 1321 default: return INVALID_IDX(idx); 1322 } 1323} 1324static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } 1325 1326static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } 1327 1328static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); } 1329#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff 1330#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0 1331static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val) 1332{ 1333 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK; 1334} 1335#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000 1336#define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000 1337 1338static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); } 1339 1340static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); } 1341#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff 1342#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0 1343static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val) 1344{ 1345 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK; 1346} 1347#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000 1348#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16 1349static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val) 1350{ 1351 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK; 1352} 1353 1354static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); } 1355 1356static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); } 1357#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff 1358#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0 1359static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val) 1360{ 1361 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK; 1362} 1363#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000 1364#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16 1365static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val) 1366{ 1367 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK; 1368} 1369 1370static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } 1371#define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff 1372#define MDP5_PP_SYNC_THRESH_START__SHIFT 0 1373static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val) 1374{ 1375 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK; 1376} 1377#define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000 1378#define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16 1379static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val) 1380{ 1381 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK; 1382} 1383 1384static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } 1385 1386static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } 1387 1388static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } 1389 1390static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); } 1391 1392static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); } 1393 1394static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); } 1395 1396static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } 1397 1398static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); } 1399 1400static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); } 1401 1402static inline uint32_t __offset_WB(uint32_t idx) 1403{ 1404 switch (idx) { 1405#if 0 /* TEMPORARY until patch that adds wb.base[] is merged */ 1406 case 0: return (mdp5_cfg->wb.base[0]); 1407 case 1: return (mdp5_cfg->wb.base[1]); 1408 case 2: return (mdp5_cfg->wb.base[2]); 1409 case 3: return (mdp5_cfg->wb.base[3]); 1410 case 4: return (mdp5_cfg->wb.base[4]); 1411#endif 1412 default: return INVALID_IDX(idx); 1413 } 1414} 1415static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } 1416 1417static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } 1418#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003 1419#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0 1420static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) 1421{ 1422 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK; 1423} 1424#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c 1425#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2 1426static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) 1427{ 1428 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK; 1429} 1430#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030 1431#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4 1432static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) 1433{ 1434 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK; 1435} 1436#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0 1437#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6 1438static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) 1439{ 1440 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK; 1441} 1442#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100 1443#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600 1444#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9 1445static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) 1446{ 1447 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK; 1448} 1449#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000 1450#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12 1451static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) 1452{ 1453 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK; 1454} 1455#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000 1456#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000 1457#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000 1458#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000 1459#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19 1460static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) 1461{ 1462 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK; 1463} 1464#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000 1465#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000 1466#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23 1467static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) 1468{ 1469 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK; 1470} 1471#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000 1472#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26 1473static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) 1474{ 1475 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK; 1476} 1477#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000 1478#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30 1479static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) 1480{ 1481 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK; 1482} 1483 1484static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } 1485#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001 1486#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006 1487#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1 1488static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) 1489{ 1490 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK; 1491} 1492#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010 1493#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4 1494static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) 1495{ 1496 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK; 1497} 1498#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020 1499#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5 1500static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) 1501{ 1502 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK; 1503} 1504#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040 1505#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100 1506#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200 1507#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9 1508static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) 1509{ 1510 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; 1511} 1512#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400 1513#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10 1514static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) 1515{ 1516 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK; 1517} 1518#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800 1519#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000 1520#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12 1521static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) 1522{ 1523 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK; 1524} 1525#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000 1526#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13 1527static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) 1528{ 1529 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK; 1530} 1531#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000 1532#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14 1533static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) 1534{ 1535 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK; 1536} 1537 1538static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); } 1539#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003 1540#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0 1541static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) 1542{ 1543 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK; 1544} 1545#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300 1546#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8 1547static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) 1548{ 1549 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK; 1550} 1551#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000 1552#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16 1553static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) 1554{ 1555 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK; 1556} 1557#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000 1558#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24 1559static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) 1560{ 1561 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK; 1562} 1563 1564static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } 1565 1566static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } 1567 1568static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } 1569 1570static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } 1571 1572static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); } 1573#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff 1574#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0 1575static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) 1576{ 1577 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK; 1578} 1579#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000 1580#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16 1581static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) 1582{ 1583 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK; 1584} 1585 1586static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); } 1587#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff 1588#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0 1589static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) 1590{ 1591 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK; 1592} 1593#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000 1594#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16 1595static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) 1596{ 1597 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK; 1598} 1599 1600static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); } 1601 1602static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); } 1603 1604static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); } 1605 1606static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); } 1607 1608static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); } 1609 1610static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); } 1611 1612static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); } 1613 1614static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); } 1615 1616static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); } 1617 1618static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); } 1619 1620static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); } 1621 1622static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } 1623#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff 1624#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0 1625static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) 1626{ 1627 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK; 1628} 1629#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000 1630#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16 1631static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) 1632{ 1633 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK; 1634} 1635 1636static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); } 1637 1638static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); } 1639#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff 1640#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0 1641static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) 1642{ 1643 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK; 1644} 1645#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000 1646#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16 1647static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) 1648{ 1649 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK; 1650} 1651 1652static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); } 1653#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff 1654#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0 1655static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) 1656{ 1657 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK; 1658} 1659#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000 1660#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16 1661static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) 1662{ 1663 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK; 1664} 1665 1666static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); } 1667#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff 1668#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0 1669static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) 1670{ 1671 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK; 1672} 1673#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000 1674#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16 1675static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) 1676{ 1677 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK; 1678} 1679 1680static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); } 1681#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff 1682#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0 1683static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) 1684{ 1685 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK; 1686} 1687#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000 1688#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16 1689static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) 1690{ 1691 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK; 1692} 1693 1694static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); } 1695#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff 1696#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0 1697static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) 1698{ 1699 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK; 1700} 1701 1702static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } 1703 1704static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } 1705#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff 1706#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0 1707static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) 1708{ 1709 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK; 1710} 1711#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00 1712#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8 1713static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) 1714{ 1715 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK; 1716} 1717 1718static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } 1719 1720static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } 1721#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff 1722#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0 1723static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) 1724{ 1725 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK; 1726} 1727#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00 1728#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8 1729static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) 1730{ 1731 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK; 1732} 1733 1734static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } 1735 1736static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } 1737#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff 1738#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0 1739static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) 1740{ 1741 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK; 1742} 1743 1744static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } 1745 1746static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } 1747#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff 1748#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0 1749static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) 1750{ 1751 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK; 1752} 1753 1754static inline uint32_t __offset_INTF(uint32_t idx) 1755{ 1756 switch (idx) { 1757 case 0: return (mdp5_cfg->intf.base[0]); 1758 case 1: return (mdp5_cfg->intf.base[1]); 1759 case 2: return (mdp5_cfg->intf.base[2]); 1760 case 3: return (mdp5_cfg->intf.base[3]); 1761 case 4: return (mdp5_cfg->intf.base[4]); 1762 default: return INVALID_IDX(idx); 1763 } 1764} 1765static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } 1766 1767static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } 1768 1769static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } 1770 1771static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } 1772#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff 1773#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0 1774static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) 1775{ 1776 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK; 1777} 1778#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000 1779#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16 1780static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) 1781{ 1782 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK; 1783} 1784 1785static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } 1786 1787static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } 1788 1789static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } 1790 1791static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } 1792 1793static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); } 1794 1795static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); } 1796 1797static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); } 1798 1799static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); } 1800 1801static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); } 1802#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff 1803#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0 1804static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) 1805{ 1806 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK; 1807} 1808#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000 1809 1810static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); } 1811#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff 1812#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0 1813static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) 1814{ 1815 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK; 1816} 1817 1818static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); } 1819 1820static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); } 1821 1822static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); } 1823#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff 1824#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0 1825static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) 1826{ 1827 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK; 1828} 1829#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000 1830#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16 1831static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) 1832{ 1833 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK; 1834} 1835 1836static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); } 1837#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff 1838#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0 1839static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) 1840{ 1841 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK; 1842} 1843#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000 1844#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16 1845static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) 1846{ 1847 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK; 1848} 1849#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000 1850 1851static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); } 1852 1853static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); } 1854 1855static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); } 1856 1857static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); } 1858#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001 1859#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002 1860#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004 1861 1862static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); } 1863 1864static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); } 1865 1866static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); } 1867 1868static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); } 1869 1870static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); } 1871 1872static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); } 1873 1874static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); } 1875 1876static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); } 1877 1878static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); } 1879 1880static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); } 1881 1882static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); } 1883 1884static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); } 1885 1886static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); } 1887 1888static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); } 1889 1890static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); } 1891 1892static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); } 1893 1894static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); } 1895 1896static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); } 1897 1898static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); } 1899 1900static inline uint32_t __offset_AD(uint32_t idx) 1901{ 1902 switch (idx) { 1903 case 0: return (mdp5_cfg->ad.base[0]); 1904 case 1: return (mdp5_cfg->ad.base[1]); 1905 default: return INVALID_IDX(idx); 1906 } 1907} 1908static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } 1909 1910static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } 1911 1912static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } 1913 1914static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } 1915 1916static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } 1917 1918static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } 1919 1920static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } 1921 1922static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } 1923 1924static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } 1925 1926static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } 1927 1928static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } 1929 1930static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } 1931 1932static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } 1933 1934static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } 1935 1936static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } 1937 1938static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } 1939 1940static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } 1941 1942static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } 1943 1944static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } 1945 1946static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } 1947 1948static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } 1949 1950static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } 1951 1952static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } 1953 1954static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } 1955 1956static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } 1957 1958static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } 1959 1960static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } 1961 1962static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } 1963 1964static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } 1965 1966static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } 1967 1968static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } 1969 1970static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } 1971 1972static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } 1973 1974static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } 1975 1976static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } 1977 1978 1979#endif /* MDP5_XML */ 1980