Searched refs:hwsp_seqno (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_timeline.c69 timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES);
97 timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;
225 u32 *hwsp_seqno = (u32 *)tl->hwsp_seqno; local
229 memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));
230 WRITE_ONCE(*hwsp_seqno, tl->seqno);
231 drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);
318 tl->hwsp_seqno = tl->hwsp_map + next_ofs;
322 GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqn
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H A Dintel_timeline_types.h47 const u32 *hwsp_seqno; member in struct:intel_timeline
H A Dselftest_engine_cs.c203 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
359 (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
360 (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
H A Dselftest_timeline.c496 if (READ_ONCE(*tl->hwsp_seqno) != tl->seqno) {
498 *tl->hwsp_seqno, tl->seqno);
584 if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
586 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
656 if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
658 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
695 const u32 *hwsp_seqno[2]; local
725 hwsp_seqno[0] = tl->hwsp_seqno;
742 hwsp_seqno[
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H A Dintel_engine_pm.c85 READ_ONCE(*ce->timeline->hwsp_seqno),
88 READ_ONCE(*ce->timeline->hwsp_seqno));
H A Dgen6_engine_cs.c378 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
398 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
H A Dgen2_engine_cs.c148 GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
H A Dselftest_rc6.c152 result = rq->hwsp_seqno + 2;
H A Dgen8_engine_cs.c434 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);
H A Dintel_engine_cs.c1352 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
2053 hwsp_seqno(rq),
H A Dintel_execlists_submission.c1987 hwsp_seqno(rq));
/linux-master/drivers/gpu/drm/i915/
H A Di915_request.h68 hwsp_seqno(rq__), ##__VA_ARGS__); \
276 * path would be rq->hw_context->ring->timeline->hwsp_seqno.
278 const u32 *hwsp_seqno; member in struct:i915_request
486 const u32 *hwsp = READ_ONCE(rq->hwsp_seqno);
492 * hwsp_seqno - the current breadcrumb value in the HW status page
495 * The emphasis in naming here is that hwsp_seqno() is not a property of the
504 static inline u32 hwsp_seqno(const struct i915_request *rq) function
629 WRITE_ONCE(rq->hwsp_seqno, /* decouple from HWSP */
697 u32 hwsp_relative_offset = offset_in_page(rq->hwsp_seqno);
703 * and combine them with the relative offset in rq->hwsp_seqno
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H A Di915_gpu_error.h113 u32 hwsp_seqno; member in struct:intel_engine_coredump::i915_gem_context_coredump
H A Di915_gpu_error.c509 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno);
1422 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ?
1423 *ce->timeline->hwsp_seqno : ~0U;
H A Di915_request.c959 rq->hwsp_seqno = tl->hwsp_seqno;

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