| /linux-master/arch/arm64/include/asm/ |
| H A D | hardirq.h | 22 u64 hcr; member in struct:nmi_ctx
55 * don't want ___ctx->hcr to be overwritten. \
58 ___ctx->hcr = ___hcr; \
70 ___hcr = ___ctx->hcr; \
72 * Make sure we read ___ctx->hcr before we release \
73 * ___ctx->cnt as it makes ___ctx->hcr updatable again. \
|
| /linux-master/drivers/usb/serial/ |
| H A D | ark3116.c | 67 __u32 hcr; /* handshake control register (0x8) member in struct:ark3116_private
145 priv->hcr = 0;
200 __u8 lcr, hcr, eval; local
215 hcr = (cflag & CRTSCTS) ? 0x03 : 0x00;
245 dev_dbg(&port->dev, "%s - setting hcr:0x%02x,lcr:0x%02x,quot:%d\n",
246 __func__, hcr, lcr, quot);
249 if (priv->hcr != hcr) {
250 priv->hcr = hcr;
[all...] |
| /linux-master/arch/arm64/kvm/hyp/include/hyp/ |
| H A D | switch.h | 276 u64 hcr = vcpu->arch.hcr_el2; local
279 hcr |= HCR_TVM;
281 write_sysreg(hcr, hcr_el2);
283 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
|
| /linux-master/drivers/infiniband/hw/mthca/ |
| H A D | mthca_cmd.c | 194 return readl(dev->hcr + HCR_STATUS_OFFSET) &
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
261 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
262 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
270 op), dev->hcr + 6 * 4);
367 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
369 __raw_readl(dev->hcr
[all...] |
| H A D | mthca_dev.h | 322 void __iomem *hcr; member in struct:mthca_dev
|
| /linux-master/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | cmd.c | 425 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
437 u32 __iomem *hcr = cmd->hcr; local
482 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
483 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
484 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
485 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
486 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
487 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
496 op), hcr
581 void __iomem *hcr = priv->cmd.hcr; local
[all...] |
| H A D | mlx4.h | 632 void __iomem *hcr; member in struct:mlx4_cmd
|
| /linux-master/drivers/atm/ |
| H A D | fore200e.c | 455 if (irq_posted && (readl(fore200e->regs.pca.hcr) & PCA200E_HCR_OUTFULL)) {
467 writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr);
474 writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr);
476 writel(0, fore200e->regs.pca.hcr);
494 fore200e->regs.pca.hcr = fore200e->virt_base + PCA200E_HCR_OFFSET;
644 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; local
645 fore200e->bus->write(hcr | SBA200E_HCR_INTR_ENA, fore200e->regs.sba.hcr);
650 return fore200e->bus->read(fore200e->regs.sba.hcr)
655 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; local
[all...] |
| H A D | fore200e.h | 773 volatile u32 __iomem * hcr; /* address of host control register */ member in struct:fore200e_pca_regs
782 u32 __iomem *hcr; /* address of host control register */ member in struct:fore200e_sba_regs
|
| /linux-master/arch/arm64/kvm/hyp/ |
| H A D | vgic-v3-sr.c | 723 u32 hcr; local
725 hcr = read_gicreg(ICH_HCR_EL2);
726 hcr += 1 << ICH_HCR_EOIcount_SHIFT;
727 write_gicreg(hcr, ICH_HCR_EL2);
|
| /linux-master/arch/arm64/kvm/ |
| H A D | arm.c | 1177 unsigned long *hcr; local
1184 hcr = vcpu_hcr(vcpu);
1186 set = test_and_set_bit(bit_index, hcr);
1188 set = test_and_clear_bit(bit_index, hcr);
|
| H A D | mmu.c | 2103 unsigned long hcr = *vcpu_hcr(vcpu); local
2114 if (!(hcr & HCR_TVM)) {
2118 *vcpu_hcr(vcpu) = hcr | HCR_TVM;
|