Searched refs:gpu_addr (Results 1 - 19 of 19) sorted by path

/freebsd-11-stable/sys/dev/drm/
H A Dr600_blit.c1202 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) argument
1222 OUT_RING(gpu_addr >> 8);
1229 OUT_RING(gpu_addr >> 8);
1285 u64 gpu_addr; local
1305 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
1314 OUT_RING(gpu_addr >> 8);
1327 OUT_RING((gpu_addr + 256) >> 8);
1343 R600_SH_ACTION_ENA, 512, gpu_addr);
1347 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) argument
1353 sq_vtx_constant_word2 = (((gpu_addr >> 3
1380 set_tex_resource(drm_radeon_private_t *dev_priv, int format, int w, int h, int pitch, u64 gpu_addr) argument
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/freebsd-11-stable/sys/dev/drm2/radeon/
H A Devergreen_blit_kms.c43 int w, int h, u64 gpu_addr)
61 radeon_ring_write(ring, gpu_addr >> 8);
113 u64 gpu_addr; local
116 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
119 radeon_ring_write(ring, gpu_addr >> 8);
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
127 radeon_ring_write(ring, gpu_addr >> 8);
132 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
133 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
138 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) argument
42 set_render_target(struct radeon_device *rdev, int format, int w, int h, u64 gpu_addr) argument
181 set_tex_resource(struct radeon_device *rdev, int format, int w, int h, int pitch, u64 gpu_addr, u32 size) argument
292 u64 gpu_addr; local
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H A Dni.c925 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
966 (ib->gpu_addr & 0xFFFFFFFC));
967 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1163 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1171 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1246 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1247 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1328 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1330 ((rdev->wb.gpu_addr
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H A Dr100.c1164 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1165 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1174 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1175 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
3788 radeon_ring_write(ring, ib->gpu_addr);
H A Dr600.c1076 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1235 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
2263 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2264 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2265 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2277 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2391 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2393 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2398 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2534 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr
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H A Dradeon.h224 uint64_t gpu_addr; member in struct:radeon_fence_driver
400 uint64_t gpu_addr; member in struct:radeon_sa_manager
449 uint64_t gpu_addr; member in struct:radeon_semaphore
635 uint64_t gpu_addr; member in struct:radeon_ib
662 uint64_t gpu_addr; member in struct:radeon_ring
737 uint64_t gpu_addr; member in struct:r600_ih
745 int w, int h, u64 gpu_addr);
750 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
753 u64 gpu_addr, u32 size);
913 uint64_t gpu_addr; member in struct:radeon_wb
1502 u64 gpu_addr; member in struct:r600_vram_scratch
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H A Dradeon_cursor.c128 uint64_t gpu_addr)
135 upper_32_bits(gpu_addr));
137 gpu_addr & 0xffffffff);
141 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
143 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
146 gpu_addr & 0xffffffff);
148 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
164 uint64_t gpu_addr; local
192 &gpu_addr);
201 radeon_set_cursor(crtc, obj, gpu_addr);
127 radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, uint64_t gpu_addr) argument
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H A Dradeon_device.c267 &rdev->wb.gpu_addr);
H A Dradeon_fence.c836 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
840 ring, (uintmax_t)rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
860 rdev->fence_drv[ring].gpu_addr = 0;
H A Dradeon_gart.c157 uint64_t gpu_addr; local
164 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
173 rdev->gart.table_addr = gpu_addr;
H A Dradeon_object.c223 u64 *gpu_addr)
229 if (gpu_addr)
230 *gpu_addr = radeon_bo_gpu_offset(bo);
270 if (gpu_addr != NULL)
271 *gpu_addr = radeon_bo_gpu_offset(bo);
278 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) argument
280 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
222 radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, u64 *gpu_addr) argument
H A Dradeon_object.h131 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
133 u64 max_offset, u64 *gpu_addr);
163 return sa_bo->manager->gpu_addr + sa_bo->soffset;
H A Dradeon_ring.c89 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
91 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
716 &ring->gpu_addr);
737 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
H A Dradeon_sa.c118 r = radeon_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
H A Dradeon_semaphore.c56 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo);
104 rdev->ring[signaler].last_semaphore_signal_addr = semaphore->gpu_addr;
105 rdev->ring[waiter].last_semaphore_wait_addr = semaphore->gpu_addr;
H A Drv770.c288 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
H A Dsi.c1800 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1862 (ib->gpu_addr & 0xFFFFFFFC));
1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2051 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2069 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2082 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2102 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2108 WREG32(CP_RB1_BASE, ring->gpu_addr >>
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H A Devergreen.c1566 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1632 (ib->gpu_addr & 0xFFFFFFFC));
1633 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1776 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1777 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1778 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1790 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3392 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3436 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3437 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr)
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H A Dr600_blit_kms.c74 int w, int h, u64 gpu_addr)
92 radeon_ring_write(ring, gpu_addr >> 8);
150 u64 gpu_addr; local
157 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
160 radeon_ring_write(ring, gpu_addr >> 8);
171 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
174 radeon_ring_write(ring, gpu_addr >> 8);
188 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
189 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
194 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) argument
73 set_render_target(struct radeon_device *rdev, int format, int w, int h, u64 gpu_addr) argument
229 set_tex_resource(struct radeon_device *rdev, int format, int w, int h, int pitch, u64 gpu_addr, u32 size) argument
324 u64 gpu_addr; local
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