drm2/radeon/r600.c

1076 	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1235 			  RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
2263 	       ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2264 	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2265 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2277 	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2391 	       upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2393 	       ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2398 	WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2534 	radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2535 	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2566 		u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2612 	uint64_t addr = semaphore->gpu_addr;
2641 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2668 	u64 addr = semaphore->gpu_addr;
3081 			  (ib->gpu_addr & 0xFFFFFFFC));
3082 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3171 	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3172 	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3233 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3234 	radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3283 				  &rdev->ih.gpu_addr);
3508 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3518 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3529 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3530 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);