1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2009 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2009 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice (including the next 13254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 14254885Sdumbbell * Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22254885Sdumbbell * DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell */ 25254885Sdumbbell 26254885Sdumbbell#include <sys/cdefs.h> 27254885Sdumbbell__FBSDID("$FreeBSD: stable/11/sys/dev/drm2/radeon/r600_blit_kms.c 342691 2019-01-02 16:28:56Z markj $"); 28254885Sdumbbell 29254885Sdumbbell#include <dev/drm2/drmP.h> 30254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 31254885Sdumbbell#include "radeon.h" 32254885Sdumbbell#include "radeon_asic.h" 33254885Sdumbbell 34254885Sdumbbell#include "r600d.h" 35254885Sdumbbell#include "r600_blit_shaders.h" 36254885Sdumbbell#include "radeon_blit_common.h" 37254885Sdumbbell 38342691Smarkj/* 23 bits of float fractional data */ 39342691Smarkj#define I2F_FRAC_BITS 23 40342691Smarkj#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1) 41342691Smarkj 42342691Smarkj/* 43342691Smarkj * Converts unsigned integer into 32-bit IEEE floating point representation. 44342691Smarkj * Will be exact from 0 to 2^24. Above that, we round towards zero 45342691Smarkj * as the fractional bits will not fit in a float. (It would be better to 46342691Smarkj * round towards even as the fpu does, but that is slower.) 47342691Smarkj * 48342691Smarkj * Moved from r600_blit.c after that file was removed. 49342691Smarkj */ 50342691Smarkj__pure uint32_t int2float(uint32_t x) 51342691Smarkj{ 52342691Smarkj uint32_t msb, exponent, fraction; 53342691Smarkj 54342691Smarkj /* Zero is special */ 55342691Smarkj if (!x) return 0; 56342691Smarkj 57342691Smarkj /* Get location of the most significant bit */ 58342691Smarkj msb = fls(x); 59342691Smarkj 60342691Smarkj /* 61342691Smarkj * Use a rotate instead of a shift because that works both leftwards 62342691Smarkj * and rightwards due to the mod(32) behaviour. This means we don't 63342691Smarkj * need to check to see if we are above 2^24 or not. 64342691Smarkj */ 65342691Smarkj fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK; 66342691Smarkj exponent = (127 + msb) << I2F_FRAC_BITS; 67342691Smarkj 68342691Smarkj return fraction + exponent; 69342691Smarkj} 70342691Smarkj 71254885Sdumbbell/* emits 21 on rv770+, 23 on r600 */ 72254885Sdumbbellstatic void 73254885Sdumbbellset_render_target(struct radeon_device *rdev, int format, 74254885Sdumbbell int w, int h, u64 gpu_addr) 75254885Sdumbbell{ 76254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 77254885Sdumbbell u32 cb_color_info; 78254885Sdumbbell int pitch, slice; 79254885Sdumbbell 80254885Sdumbbell h = roundup2(h, 8); 81254885Sdumbbell if (h < 8) 82254885Sdumbbell h = 8; 83254885Sdumbbell 84254885Sdumbbell cb_color_info = CB_FORMAT(format) | 85254885Sdumbbell CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | 86254885Sdumbbell CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); 87254885Sdumbbell pitch = (w / 8) - 1; 88254885Sdumbbell slice = ((w * h) / 64) - 1; 89254885Sdumbbell 90254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 91254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 92254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 93254885Sdumbbell 94254885Sdumbbell if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { 95254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); 96254885Sdumbbell radeon_ring_write(ring, 2 << 0); 97254885Sdumbbell } 98254885Sdumbbell 99254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 100254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 101254885Sdumbbell radeon_ring_write(ring, (pitch << 0) | (slice << 10)); 102254885Sdumbbell 103254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 104254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 105254885Sdumbbell radeon_ring_write(ring, 0); 106254885Sdumbbell 107254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 108254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 109254885Sdumbbell radeon_ring_write(ring, cb_color_info); 110254885Sdumbbell 111254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 112254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 113254885Sdumbbell radeon_ring_write(ring, 0); 114254885Sdumbbell 115254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 116254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 117254885Sdumbbell radeon_ring_write(ring, 0); 118254885Sdumbbell 119254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 120254885Sdumbbell radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 121254885Sdumbbell radeon_ring_write(ring, 0); 122254885Sdumbbell} 123254885Sdumbbell 124254885Sdumbbell/* emits 5dw */ 125254885Sdumbbellstatic void 126254885Sdumbbellcp_set_surface_sync(struct radeon_device *rdev, 127254885Sdumbbell u32 sync_type, u32 size, 128254885Sdumbbell u64 mc_addr) 129254885Sdumbbell{ 130254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 131254885Sdumbbell u32 cp_coher_size; 132254885Sdumbbell 133254885Sdumbbell if (size == 0xffffffff) 134254885Sdumbbell cp_coher_size = 0xffffffff; 135254885Sdumbbell else 136254885Sdumbbell cp_coher_size = ((size + 255) >> 8); 137254885Sdumbbell 138254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 139254885Sdumbbell radeon_ring_write(ring, sync_type); 140254885Sdumbbell radeon_ring_write(ring, cp_coher_size); 141254885Sdumbbell radeon_ring_write(ring, mc_addr >> 8); 142254885Sdumbbell radeon_ring_write(ring, 10); /* poll interval */ 143254885Sdumbbell} 144254885Sdumbbell 145254885Sdumbbell/* emits 21dw + 1 surface sync = 26dw */ 146254885Sdumbbellstatic void 147254885Sdumbbellset_shaders(struct radeon_device *rdev) 148254885Sdumbbell{ 149254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 150254885Sdumbbell u64 gpu_addr; 151254885Sdumbbell u32 sq_pgm_resources; 152254885Sdumbbell 153254885Sdumbbell /* setup shader regs */ 154254885Sdumbbell sq_pgm_resources = (1 << 0); 155254885Sdumbbell 156254885Sdumbbell /* VS */ 157254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 158254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 159254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 160254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 161254885Sdumbbell 162254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 163254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 164254885Sdumbbell radeon_ring_write(ring, sq_pgm_resources); 165254885Sdumbbell 166254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 167254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 168254885Sdumbbell radeon_ring_write(ring, 0); 169254885Sdumbbell 170254885Sdumbbell /* PS */ 171254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; 172254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 173254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 174254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 175254885Sdumbbell 176254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 177254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 178254885Sdumbbell radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); 179254885Sdumbbell 180254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 181254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 182254885Sdumbbell radeon_ring_write(ring, 2); 183254885Sdumbbell 184254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 185254885Sdumbbell radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 186254885Sdumbbell radeon_ring_write(ring, 0); 187254885Sdumbbell 188254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 189254885Sdumbbell cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); 190254885Sdumbbell} 191254885Sdumbbell 192254885Sdumbbell/* emits 9 + 1 sync (5) = 14*/ 193254885Sdumbbellstatic void 194254885Sdumbbellset_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 195254885Sdumbbell{ 196254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 197254885Sdumbbell u32 sq_vtx_constant_word2; 198254885Sdumbbell 199254885Sdumbbell sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | 200254885Sdumbbell SQ_VTXC_STRIDE(16); 201254885Sdumbbell#ifdef __BIG_ENDIAN 202254885Sdumbbell sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); 203254885Sdumbbell#endif 204254885Sdumbbell 205254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); 206254885Sdumbbell radeon_ring_write(ring, 0x460); 207254885Sdumbbell radeon_ring_write(ring, gpu_addr & 0xffffffff); 208254885Sdumbbell radeon_ring_write(ring, 48 - 1); 209254885Sdumbbell radeon_ring_write(ring, sq_vtx_constant_word2); 210254885Sdumbbell radeon_ring_write(ring, 1 << 0); 211254885Sdumbbell radeon_ring_write(ring, 0); 212254885Sdumbbell radeon_ring_write(ring, 0); 213254885Sdumbbell radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30); 214254885Sdumbbell 215254885Sdumbbell if ((rdev->family == CHIP_RV610) || 216254885Sdumbbell (rdev->family == CHIP_RV620) || 217254885Sdumbbell (rdev->family == CHIP_RS780) || 218254885Sdumbbell (rdev->family == CHIP_RS880) || 219254885Sdumbbell (rdev->family == CHIP_RV710)) 220254885Sdumbbell cp_set_surface_sync(rdev, 221254885Sdumbbell PACKET3_TC_ACTION_ENA, 48, gpu_addr); 222254885Sdumbbell else 223254885Sdumbbell cp_set_surface_sync(rdev, 224254885Sdumbbell PACKET3_VC_ACTION_ENA, 48, gpu_addr); 225254885Sdumbbell} 226254885Sdumbbell 227254885Sdumbbell/* emits 9 */ 228254885Sdumbbellstatic void 229254885Sdumbbellset_tex_resource(struct radeon_device *rdev, 230254885Sdumbbell int format, int w, int h, int pitch, 231254885Sdumbbell u64 gpu_addr, u32 size) 232254885Sdumbbell{ 233254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 234254885Sdumbbell uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; 235254885Sdumbbell 236254885Sdumbbell if (h < 1) 237254885Sdumbbell h = 1; 238254885Sdumbbell 239254885Sdumbbell sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) | 240254885Sdumbbell S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 241254885Sdumbbell sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) | 242254885Sdumbbell S_038000_TEX_WIDTH(w - 1); 243254885Sdumbbell 244254885Sdumbbell sq_tex_resource_word1 = S_038004_DATA_FORMAT(format); 245254885Sdumbbell sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1); 246254885Sdumbbell 247254885Sdumbbell sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) | 248254885Sdumbbell S_038010_DST_SEL_X(SQ_SEL_X) | 249254885Sdumbbell S_038010_DST_SEL_Y(SQ_SEL_Y) | 250254885Sdumbbell S_038010_DST_SEL_Z(SQ_SEL_Z) | 251254885Sdumbbell S_038010_DST_SEL_W(SQ_SEL_W); 252254885Sdumbbell 253254885Sdumbbell cp_set_surface_sync(rdev, 254254885Sdumbbell PACKET3_TC_ACTION_ENA, size, gpu_addr); 255254885Sdumbbell 256254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); 257254885Sdumbbell radeon_ring_write(ring, 0); 258254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word0); 259254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word1); 260254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 261254885Sdumbbell radeon_ring_write(ring, gpu_addr >> 8); 262254885Sdumbbell radeon_ring_write(ring, sq_tex_resource_word4); 263254885Sdumbbell radeon_ring_write(ring, 0); 264254885Sdumbbell radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30); 265254885Sdumbbell} 266254885Sdumbbell 267254885Sdumbbell/* emits 12 */ 268254885Sdumbbellstatic void 269254885Sdumbbellset_scissors(struct radeon_device *rdev, int x1, int y1, 270254885Sdumbbell int x2, int y2) 271254885Sdumbbell{ 272254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 273254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 274254885Sdumbbell radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 275254885Sdumbbell radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); 276254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 277254885Sdumbbell 278254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 279254885Sdumbbell radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 280258780Seadler radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); 281254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 282254885Sdumbbell 283254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 284254885Sdumbbell radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 285258780Seadler radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31)); 286254885Sdumbbell radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); 287254885Sdumbbell} 288254885Sdumbbell 289254885Sdumbbell/* emits 10 */ 290254885Sdumbbellstatic void 291254885Sdumbbelldraw_auto(struct radeon_device *rdev) 292254885Sdumbbell{ 293254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 294254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 295254885Sdumbbell radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 296254885Sdumbbell radeon_ring_write(ring, DI_PT_RECTLIST); 297254885Sdumbbell 298254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); 299254885Sdumbbell radeon_ring_write(ring, 300254885Sdumbbell#ifdef __BIG_ENDIAN 301254885Sdumbbell (2 << 2) | 302254885Sdumbbell#endif 303254885Sdumbbell DI_INDEX_SIZE_16_BIT); 304254885Sdumbbell 305254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); 306254885Sdumbbell radeon_ring_write(ring, 1); 307254885Sdumbbell 308254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); 309254885Sdumbbell radeon_ring_write(ring, 3); 310254885Sdumbbell radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); 311254885Sdumbbell 312254885Sdumbbell} 313254885Sdumbbell 314254885Sdumbbell/* emits 14 */ 315254885Sdumbbellstatic void 316254885Sdumbbellset_default_state(struct radeon_device *rdev) 317254885Sdumbbell{ 318254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 319254885Sdumbbell u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 320254885Sdumbbell u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 321254885Sdumbbell int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; 322254885Sdumbbell int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; 323254885Sdumbbell int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; 324254885Sdumbbell u64 gpu_addr; 325254885Sdumbbell int dwords; 326254885Sdumbbell 327254885Sdumbbell switch (rdev->family) { 328254885Sdumbbell case CHIP_R600: 329254885Sdumbbell num_ps_gprs = 192; 330254885Sdumbbell num_vs_gprs = 56; 331254885Sdumbbell num_temp_gprs = 4; 332254885Sdumbbell num_gs_gprs = 0; 333254885Sdumbbell num_es_gprs = 0; 334254885Sdumbbell num_ps_threads = 136; 335254885Sdumbbell num_vs_threads = 48; 336254885Sdumbbell num_gs_threads = 4; 337254885Sdumbbell num_es_threads = 4; 338254885Sdumbbell num_ps_stack_entries = 128; 339254885Sdumbbell num_vs_stack_entries = 128; 340254885Sdumbbell num_gs_stack_entries = 0; 341254885Sdumbbell num_es_stack_entries = 0; 342254885Sdumbbell break; 343254885Sdumbbell case CHIP_RV630: 344254885Sdumbbell case CHIP_RV635: 345254885Sdumbbell num_ps_gprs = 84; 346254885Sdumbbell num_vs_gprs = 36; 347254885Sdumbbell num_temp_gprs = 4; 348254885Sdumbbell num_gs_gprs = 0; 349254885Sdumbbell num_es_gprs = 0; 350254885Sdumbbell num_ps_threads = 144; 351254885Sdumbbell num_vs_threads = 40; 352254885Sdumbbell num_gs_threads = 4; 353254885Sdumbbell num_es_threads = 4; 354254885Sdumbbell num_ps_stack_entries = 40; 355254885Sdumbbell num_vs_stack_entries = 40; 356254885Sdumbbell num_gs_stack_entries = 32; 357254885Sdumbbell num_es_stack_entries = 16; 358254885Sdumbbell break; 359254885Sdumbbell case CHIP_RV610: 360254885Sdumbbell case CHIP_RV620: 361254885Sdumbbell case CHIP_RS780: 362254885Sdumbbell case CHIP_RS880: 363254885Sdumbbell default: 364254885Sdumbbell num_ps_gprs = 84; 365254885Sdumbbell num_vs_gprs = 36; 366254885Sdumbbell num_temp_gprs = 4; 367254885Sdumbbell num_gs_gprs = 0; 368254885Sdumbbell num_es_gprs = 0; 369254885Sdumbbell num_ps_threads = 136; 370254885Sdumbbell num_vs_threads = 48; 371254885Sdumbbell num_gs_threads = 4; 372254885Sdumbbell num_es_threads = 4; 373254885Sdumbbell num_ps_stack_entries = 40; 374254885Sdumbbell num_vs_stack_entries = 40; 375254885Sdumbbell num_gs_stack_entries = 32; 376254885Sdumbbell num_es_stack_entries = 16; 377254885Sdumbbell break; 378254885Sdumbbell case CHIP_RV670: 379254885Sdumbbell num_ps_gprs = 144; 380254885Sdumbbell num_vs_gprs = 40; 381254885Sdumbbell num_temp_gprs = 4; 382254885Sdumbbell num_gs_gprs = 0; 383254885Sdumbbell num_es_gprs = 0; 384254885Sdumbbell num_ps_threads = 136; 385254885Sdumbbell num_vs_threads = 48; 386254885Sdumbbell num_gs_threads = 4; 387254885Sdumbbell num_es_threads = 4; 388254885Sdumbbell num_ps_stack_entries = 40; 389254885Sdumbbell num_vs_stack_entries = 40; 390254885Sdumbbell num_gs_stack_entries = 32; 391254885Sdumbbell num_es_stack_entries = 16; 392254885Sdumbbell break; 393254885Sdumbbell case CHIP_RV770: 394254885Sdumbbell num_ps_gprs = 192; 395254885Sdumbbell num_vs_gprs = 56; 396254885Sdumbbell num_temp_gprs = 4; 397254885Sdumbbell num_gs_gprs = 0; 398254885Sdumbbell num_es_gprs = 0; 399254885Sdumbbell num_ps_threads = 188; 400254885Sdumbbell num_vs_threads = 60; 401254885Sdumbbell num_gs_threads = 0; 402254885Sdumbbell num_es_threads = 0; 403254885Sdumbbell num_ps_stack_entries = 256; 404254885Sdumbbell num_vs_stack_entries = 256; 405254885Sdumbbell num_gs_stack_entries = 0; 406254885Sdumbbell num_es_stack_entries = 0; 407254885Sdumbbell break; 408254885Sdumbbell case CHIP_RV730: 409254885Sdumbbell case CHIP_RV740: 410254885Sdumbbell num_ps_gprs = 84; 411254885Sdumbbell num_vs_gprs = 36; 412254885Sdumbbell num_temp_gprs = 4; 413254885Sdumbbell num_gs_gprs = 0; 414254885Sdumbbell num_es_gprs = 0; 415254885Sdumbbell num_ps_threads = 188; 416254885Sdumbbell num_vs_threads = 60; 417254885Sdumbbell num_gs_threads = 0; 418254885Sdumbbell num_es_threads = 0; 419254885Sdumbbell num_ps_stack_entries = 128; 420254885Sdumbbell num_vs_stack_entries = 128; 421254885Sdumbbell num_gs_stack_entries = 0; 422254885Sdumbbell num_es_stack_entries = 0; 423254885Sdumbbell break; 424254885Sdumbbell case CHIP_RV710: 425254885Sdumbbell num_ps_gprs = 192; 426254885Sdumbbell num_vs_gprs = 56; 427254885Sdumbbell num_temp_gprs = 4; 428254885Sdumbbell num_gs_gprs = 0; 429254885Sdumbbell num_es_gprs = 0; 430254885Sdumbbell num_ps_threads = 144; 431254885Sdumbbell num_vs_threads = 48; 432254885Sdumbbell num_gs_threads = 0; 433254885Sdumbbell num_es_threads = 0; 434254885Sdumbbell num_ps_stack_entries = 128; 435254885Sdumbbell num_vs_stack_entries = 128; 436254885Sdumbbell num_gs_stack_entries = 0; 437254885Sdumbbell num_es_stack_entries = 0; 438254885Sdumbbell break; 439254885Sdumbbell } 440254885Sdumbbell 441254885Sdumbbell if ((rdev->family == CHIP_RV610) || 442254885Sdumbbell (rdev->family == CHIP_RV620) || 443254885Sdumbbell (rdev->family == CHIP_RS780) || 444254885Sdumbbell (rdev->family == CHIP_RS880) || 445254885Sdumbbell (rdev->family == CHIP_RV710)) 446254885Sdumbbell sq_config = 0; 447254885Sdumbbell else 448254885Sdumbbell sq_config = VC_ENABLE; 449254885Sdumbbell 450254885Sdumbbell sq_config |= (DX9_CONSTS | 451254885Sdumbbell ALU_INST_PREFER_VECTOR | 452254885Sdumbbell PS_PRIO(0) | 453254885Sdumbbell VS_PRIO(1) | 454254885Sdumbbell GS_PRIO(2) | 455254885Sdumbbell ES_PRIO(3)); 456254885Sdumbbell 457254885Sdumbbell sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | 458254885Sdumbbell NUM_VS_GPRS(num_vs_gprs) | 459254885Sdumbbell NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); 460254885Sdumbbell sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | 461254885Sdumbbell NUM_ES_GPRS(num_es_gprs)); 462254885Sdumbbell sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | 463254885Sdumbbell NUM_VS_THREADS(num_vs_threads) | 464254885Sdumbbell NUM_GS_THREADS(num_gs_threads) | 465254885Sdumbbell NUM_ES_THREADS(num_es_threads)); 466254885Sdumbbell sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | 467254885Sdumbbell NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); 468254885Sdumbbell sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | 469254885Sdumbbell NUM_ES_STACK_ENTRIES(num_es_stack_entries)); 470254885Sdumbbell 471254885Sdumbbell /* emit an IB pointing at default state */ 472254885Sdumbbell dwords = roundup2(rdev->r600_blit.state_len, 0x10); 473254885Sdumbbell gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 474254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 475254885Sdumbbell radeon_ring_write(ring, 476254885Sdumbbell#ifdef __BIG_ENDIAN 477254885Sdumbbell (2 << 0) | 478254885Sdumbbell#endif 479254885Sdumbbell (gpu_addr & 0xFFFFFFFC)); 480254885Sdumbbell radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); 481254885Sdumbbell radeon_ring_write(ring, dwords); 482254885Sdumbbell 483254885Sdumbbell /* SQ config */ 484254885Sdumbbell radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 485254885Sdumbbell radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 486254885Sdumbbell radeon_ring_write(ring, sq_config); 487254885Sdumbbell radeon_ring_write(ring, sq_gpr_resource_mgmt_1); 488254885Sdumbbell radeon_ring_write(ring, sq_gpr_resource_mgmt_2); 489254885Sdumbbell radeon_ring_write(ring, sq_thread_resource_mgmt); 490254885Sdumbbell radeon_ring_write(ring, sq_stack_resource_mgmt_1); 491254885Sdumbbell radeon_ring_write(ring, sq_stack_resource_mgmt_2); 492254885Sdumbbell} 493254885Sdumbbell 494254885Sdumbbellint r600_blit_init(struct radeon_device *rdev) 495254885Sdumbbell{ 496254885Sdumbbell u32 obj_size; 497254885Sdumbbell int i, r, dwords; 498254885Sdumbbell void *ptr; 499254885Sdumbbell u32 packet2s[16]; 500254885Sdumbbell int num_packet2s = 0; 501254885Sdumbbell 502254885Sdumbbell rdev->r600_blit.primitives.set_render_target = set_render_target; 503254885Sdumbbell rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; 504254885Sdumbbell rdev->r600_blit.primitives.set_shaders = set_shaders; 505254885Sdumbbell rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; 506254885Sdumbbell rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; 507254885Sdumbbell rdev->r600_blit.primitives.set_scissors = set_scissors; 508254885Sdumbbell rdev->r600_blit.primitives.draw_auto = draw_auto; 509254885Sdumbbell rdev->r600_blit.primitives.set_default_state = set_default_state; 510254885Sdumbbell 511254885Sdumbbell rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ 512254885Sdumbbell rdev->r600_blit.ring_size_common += 40; /* shaders + def state */ 513254885Sdumbbell rdev->r600_blit.ring_size_common += 5; /* done copy */ 514254885Sdumbbell rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ 515254885Sdumbbell 516254885Sdumbbell rdev->r600_blit.ring_size_per_loop = 76; 517254885Sdumbbell /* set_render_target emits 2 extra dwords on rv6xx */ 518254885Sdumbbell if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) 519254885Sdumbbell rdev->r600_blit.ring_size_per_loop += 2; 520254885Sdumbbell 521254885Sdumbbell rdev->r600_blit.max_dim = 8192; 522254885Sdumbbell 523254885Sdumbbell rdev->r600_blit.state_offset = 0; 524254885Sdumbbell 525254885Sdumbbell if (rdev->family >= CHIP_RV770) 526254885Sdumbbell rdev->r600_blit.state_len = r7xx_default_size; 527254885Sdumbbell else 528254885Sdumbbell rdev->r600_blit.state_len = r6xx_default_size; 529254885Sdumbbell 530254885Sdumbbell dwords = rdev->r600_blit.state_len; 531254885Sdumbbell while (dwords & 0xf) { 532254885Sdumbbell packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); 533254885Sdumbbell dwords++; 534254885Sdumbbell } 535254885Sdumbbell 536254885Sdumbbell obj_size = dwords * 4; 537254885Sdumbbell obj_size = roundup2(obj_size, 256); 538254885Sdumbbell 539254885Sdumbbell rdev->r600_blit.vs_offset = obj_size; 540254885Sdumbbell obj_size += r6xx_vs_size * 4; 541254885Sdumbbell obj_size = roundup2(obj_size, 256); 542254885Sdumbbell 543254885Sdumbbell rdev->r600_blit.ps_offset = obj_size; 544254885Sdumbbell obj_size += r6xx_ps_size * 4; 545254885Sdumbbell obj_size = roundup2(obj_size, 256); 546254885Sdumbbell 547254885Sdumbbell /* pin copy shader into vram if not already initialized */ 548254885Sdumbbell if (rdev->r600_blit.shader_obj == NULL) { 549254885Sdumbbell r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, 550254885Sdumbbell RADEON_GEM_DOMAIN_VRAM, 551254885Sdumbbell NULL, &rdev->r600_blit.shader_obj); 552254885Sdumbbell if (r) { 553254885Sdumbbell DRM_ERROR("r600 failed to allocate shader\n"); 554254885Sdumbbell return r; 555254885Sdumbbell } 556254885Sdumbbell 557254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 558254885Sdumbbell if (unlikely(r != 0)) 559254885Sdumbbell return r; 560254885Sdumbbell r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 561254885Sdumbbell &rdev->r600_blit.shader_gpu_addr); 562254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 563254885Sdumbbell if (r) { 564254885Sdumbbell dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 565254885Sdumbbell return r; 566254885Sdumbbell } 567254885Sdumbbell } 568254885Sdumbbell 569254885Sdumbbell DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", 570254885Sdumbbell obj_size, 571254885Sdumbbell rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); 572254885Sdumbbell 573254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 574254885Sdumbbell if (unlikely(r != 0)) 575254885Sdumbbell return r; 576254885Sdumbbell r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); 577254885Sdumbbell if (r) { 578254885Sdumbbell DRM_ERROR("failed to map blit object %d\n", r); 579254885Sdumbbell return r; 580254885Sdumbbell } 581254885Sdumbbell if (rdev->family >= CHIP_RV770) 582254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset, 583254885Sdumbbell r7xx_default_state, rdev->r600_blit.state_len * 4); 584254885Sdumbbell else 585254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset, 586254885Sdumbbell r6xx_default_state, rdev->r600_blit.state_len * 4); 587254885Sdumbbell if (num_packet2s) 588254885Sdumbbell memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 589254885Sdumbbell packet2s, num_packet2s * 4); 590254885Sdumbbell for (i = 0; i < r6xx_vs_size; i++) 591254885Sdumbbell *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]); 592254885Sdumbbell for (i = 0; i < r6xx_ps_size; i++) 593254885Sdumbbell *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); 594254885Sdumbbell radeon_bo_kunmap(rdev->r600_blit.shader_obj); 595254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 596254885Sdumbbell 597254885Sdumbbell radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 598254885Sdumbbell return 0; 599254885Sdumbbell} 600254885Sdumbbell 601254885Sdumbbellvoid r600_blit_fini(struct radeon_device *rdev) 602254885Sdumbbell{ 603254885Sdumbbell int r; 604254885Sdumbbell 605254885Sdumbbell radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 606254885Sdumbbell if (rdev->r600_blit.shader_obj == NULL) 607254885Sdumbbell return; 608254885Sdumbbell /* If we can't reserve the bo, unref should be enough to destroy 609254885Sdumbbell * it when it becomes idle. 610254885Sdumbbell */ 611254885Sdumbbell r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 612254885Sdumbbell if (!r) { 613254885Sdumbbell radeon_bo_unpin(rdev->r600_blit.shader_obj); 614254885Sdumbbell radeon_bo_unreserve(rdev->r600_blit.shader_obj); 615254885Sdumbbell } 616254885Sdumbbell radeon_bo_unref(&rdev->r600_blit.shader_obj); 617254885Sdumbbell} 618254885Sdumbbell 619254885Sdumbbellstatic unsigned r600_blit_create_rect(unsigned num_gpu_pages, 620254885Sdumbbell int *width, int *height, int max_dim) 621254885Sdumbbell{ 622254885Sdumbbell unsigned max_pages; 623254885Sdumbbell unsigned pages = num_gpu_pages; 624254885Sdumbbell int w, h; 625254885Sdumbbell 626254885Sdumbbell if (num_gpu_pages == 0) { 627254885Sdumbbell /* not supposed to be called with no pages, but just in case */ 628254885Sdumbbell h = 0; 629254885Sdumbbell w = 0; 630254885Sdumbbell pages = 0; 631254885Sdumbbell DRM_ERROR("%s: called with no pages", __func__); 632254885Sdumbbell } else { 633254885Sdumbbell int rect_order = 2; 634254885Sdumbbell h = RECT_UNIT_H; 635254885Sdumbbell while (num_gpu_pages / rect_order) { 636254885Sdumbbell h *= 2; 637254885Sdumbbell rect_order *= 4; 638254885Sdumbbell if (h >= max_dim) { 639254885Sdumbbell h = max_dim; 640254885Sdumbbell break; 641254885Sdumbbell } 642254885Sdumbbell } 643254885Sdumbbell max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H); 644254885Sdumbbell if (pages > max_pages) 645254885Sdumbbell pages = max_pages; 646254885Sdumbbell w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h; 647254885Sdumbbell w = (w / RECT_UNIT_W) * RECT_UNIT_W; 648254885Sdumbbell pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H); 649254885Sdumbbell KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0")); 650254885Sdumbbell } 651254885Sdumbbell 652254885Sdumbbell 653254885Sdumbbell DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages); 654254885Sdumbbell 655254885Sdumbbell /* return width and height only of the caller wants it */ 656254885Sdumbbell if (height) 657254885Sdumbbell *height = h; 658254885Sdumbbell if (width) 659254885Sdumbbell *width = w; 660254885Sdumbbell 661254885Sdumbbell return pages; 662254885Sdumbbell} 663254885Sdumbbell 664254885Sdumbbell 665254885Sdumbbellint r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 666254885Sdumbbell struct radeon_fence **fence, struct radeon_sa_bo **vb, 667254885Sdumbbell struct radeon_semaphore **sem) 668254885Sdumbbell{ 669254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 670254885Sdumbbell int r; 671254885Sdumbbell int ring_size; 672254885Sdumbbell int num_loops = 0; 673254885Sdumbbell int dwords_per_loop = rdev->r600_blit.ring_size_per_loop; 674254885Sdumbbell 675254885Sdumbbell /* num loops */ 676254885Sdumbbell while (num_gpu_pages) { 677254885Sdumbbell num_gpu_pages -= 678254885Sdumbbell r600_blit_create_rect(num_gpu_pages, NULL, NULL, 679254885Sdumbbell rdev->r600_blit.max_dim); 680254885Sdumbbell num_loops++; 681254885Sdumbbell } 682254885Sdumbbell 683254885Sdumbbell /* 48 bytes for vertex per loop */ 684254885Sdumbbell r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb, 685254885Sdumbbell (num_loops*48)+256, 256, true); 686254885Sdumbbell if (r) { 687254885Sdumbbell return r; 688254885Sdumbbell } 689254885Sdumbbell 690254885Sdumbbell r = radeon_semaphore_create(rdev, sem); 691254885Sdumbbell if (r) { 692254885Sdumbbell radeon_sa_bo_free(rdev, vb, NULL); 693254885Sdumbbell return r; 694254885Sdumbbell } 695254885Sdumbbell 696254885Sdumbbell /* calculate number of loops correctly */ 697254885Sdumbbell ring_size = num_loops * dwords_per_loop; 698254885Sdumbbell ring_size += rdev->r600_blit.ring_size_common; 699254885Sdumbbell r = radeon_ring_lock(rdev, ring, ring_size); 700254885Sdumbbell if (r) { 701254885Sdumbbell radeon_sa_bo_free(rdev, vb, NULL); 702254885Sdumbbell radeon_semaphore_free(rdev, sem, NULL); 703254885Sdumbbell return r; 704254885Sdumbbell } 705254885Sdumbbell 706254885Sdumbbell if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) { 707254885Sdumbbell radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring, 708254885Sdumbbell RADEON_RING_TYPE_GFX_INDEX); 709254885Sdumbbell radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX); 710254885Sdumbbell } else { 711254885Sdumbbell radeon_semaphore_free(rdev, sem, NULL); 712254885Sdumbbell } 713254885Sdumbbell 714254885Sdumbbell rdev->r600_blit.primitives.set_default_state(rdev); 715254885Sdumbbell rdev->r600_blit.primitives.set_shaders(rdev); 716254885Sdumbbell return 0; 717254885Sdumbbell} 718254885Sdumbbell 719254885Sdumbbellvoid r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 720254885Sdumbbell struct radeon_sa_bo *vb, struct radeon_semaphore *sem) 721254885Sdumbbell{ 722254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 723254885Sdumbbell int r; 724254885Sdumbbell 725254885Sdumbbell r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 726254885Sdumbbell if (r) { 727254885Sdumbbell radeon_ring_unlock_undo(rdev, ring); 728254885Sdumbbell return; 729254885Sdumbbell } 730254885Sdumbbell 731254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 732254885Sdumbbell radeon_sa_bo_free(rdev, &vb, *fence); 733254885Sdumbbell radeon_semaphore_free(rdev, &sem, *fence); 734254885Sdumbbell} 735254885Sdumbbell 736254885Sdumbbellvoid r600_kms_blit_copy(struct radeon_device *rdev, 737254885Sdumbbell u64 src_gpu_addr, u64 dst_gpu_addr, 738254885Sdumbbell unsigned num_gpu_pages, 739254885Sdumbbell struct radeon_sa_bo *vb) 740254885Sdumbbell{ 741254885Sdumbbell u64 vb_gpu_addr; 742254885Sdumbbell u32 *vb_cpu_addr; 743254885Sdumbbell 744254885Sdumbbell DRM_DEBUG("emitting copy %16jx %16jx %d\n", 745254885Sdumbbell (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages); 746254885Sdumbbell vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb); 747254885Sdumbbell vb_gpu_addr = radeon_sa_bo_gpu_addr(vb); 748254885Sdumbbell 749254885Sdumbbell while (num_gpu_pages) { 750254885Sdumbbell int w, h; 751254885Sdumbbell unsigned size_in_bytes; 752254885Sdumbbell unsigned pages_per_loop = 753254885Sdumbbell r600_blit_create_rect(num_gpu_pages, &w, &h, 754254885Sdumbbell rdev->r600_blit.max_dim); 755254885Sdumbbell 756254885Sdumbbell size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE; 757254885Sdumbbell DRM_DEBUG("rectangle w=%d h=%d\n", w, h); 758254885Sdumbbell 759254885Sdumbbell vb_cpu_addr[0] = 0; 760254885Sdumbbell vb_cpu_addr[1] = 0; 761254885Sdumbbell vb_cpu_addr[2] = 0; 762254885Sdumbbell vb_cpu_addr[3] = 0; 763254885Sdumbbell 764254885Sdumbbell vb_cpu_addr[4] = 0; 765254885Sdumbbell vb_cpu_addr[5] = int2float(h); 766254885Sdumbbell vb_cpu_addr[6] = 0; 767254885Sdumbbell vb_cpu_addr[7] = int2float(h); 768254885Sdumbbell 769254885Sdumbbell vb_cpu_addr[8] = int2float(w); 770254885Sdumbbell vb_cpu_addr[9] = int2float(h); 771254885Sdumbbell vb_cpu_addr[10] = int2float(w); 772254885Sdumbbell vb_cpu_addr[11] = int2float(h); 773254885Sdumbbell 774254885Sdumbbell rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8, 775254885Sdumbbell w, h, w, src_gpu_addr, size_in_bytes); 776254885Sdumbbell rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8, 777254885Sdumbbell w, h, dst_gpu_addr); 778254885Sdumbbell rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h); 779254885Sdumbbell rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr); 780254885Sdumbbell rdev->r600_blit.primitives.draw_auto(rdev); 781254885Sdumbbell rdev->r600_blit.primitives.cp_set_surface_sync(rdev, 782254885Sdumbbell PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, 783254885Sdumbbell size_in_bytes, dst_gpu_addr); 784254885Sdumbbell 785254885Sdumbbell vb_cpu_addr += 12; 786254885Sdumbbell vb_gpu_addr += 4*12; 787254885Sdumbbell src_gpu_addr += size_in_bytes; 788254885Sdumbbell dst_gpu_addr += size_in_bytes; 789254885Sdumbbell num_gpu_pages -= pages_per_loop; 790254885Sdumbbell } 791254885Sdumbbell} 792