Lines Matching refs:gpu_addr
74 int w, int h, u64 gpu_addr)
92 radeon_ring_write(ring, gpu_addr >> 8);
150 u64 gpu_addr;
157 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
160 radeon_ring_write(ring, gpu_addr >> 8);
171 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
174 radeon_ring_write(ring, gpu_addr >> 8);
188 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
189 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
194 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
199 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
207 radeon_ring_write(ring, gpu_addr & 0xffffffff);
221 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
224 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
231 u64 gpu_addr, u32 size)
254 PACKET3_TC_ACTION_ENA, size, gpu_addr);
260 radeon_ring_write(ring, gpu_addr >> 8);
261 radeon_ring_write(ring, gpu_addr >> 8);
324 u64 gpu_addr;
473 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
479 (gpu_addr & 0xFFFFFFFC));
480 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);