/linux-master/virt/kvm/ |
H A D | pfncache.c | 28 struct gfn_to_pfn_cache *gpc; local 31 list_for_each_entry(gpc, &kvm->gpc_list, list) { 32 read_lock_irq(&gpc->lock); 35 if (gpc->valid && !is_error_noslot_pfn(gpc->pfn) && 36 gpc->uhva >= start && gpc->uhva < end) { 37 read_unlock_irq(&gpc->lock); 47 write_lock_irq(&gpc->lock); 48 if (gpc 73 kvm_gpc_check(struct gfn_to_pfn_cache *gpc, unsigned long len) argument 155 hva_to_pfn_retry(struct gfn_to_pfn_cache *gpc) argument 248 __kvm_gpc_refresh(struct gfn_to_pfn_cache *gpc, gpa_t gpa, unsigned long uhva) argument 358 kvm_gpc_refresh(struct gfn_to_pfn_cache *gpc, unsigned long len) argument 377 kvm_gpc_init(struct gfn_to_pfn_cache *gpc, struct kvm *kvm) argument 389 __kvm_gpc_activate(struct gfn_to_pfn_cache *gpc, gpa_t gpa, unsigned long uhva, unsigned long len) argument 419 kvm_gpc_activate(struct gfn_to_pfn_cache *gpc, gpa_t gpa, unsigned long len) argument 431 kvm_gpc_activate_hva(struct gfn_to_pfn_cache *gpc, unsigned long uhva, unsigned long len) argument 436 kvm_gpc_deactivate(struct gfn_to_pfn_cache *gpc) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | gv100.c | 28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); 33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); 42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); 44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); 45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); 49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) argument 51 gv100_gr_trap_sm(gr, gpc, tpc, 0); 52 gv100_gr_trap_sm(gr, gpc, tpc, 1); 64 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, in argument 75 gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) argument 89 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc) argument 121 u32 gpc; local 231 u32 gpc, tpc, pes, gtpc; local [all...] |
H A D | ctxgp102.c | 51 int gpc, ppc, n = 0; local 57 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 59 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 63 const u32 o = PPC_UNIT(gpc, ppc, 0); 64 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); 66 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 76 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 90 int gpc; local [all...] |
H A D | ctxgm200.c | 55 const u8 gpc = gr->sm[sm].gpc; local 57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); 58 gpcs[gpc] |= sm << (tpc * 8); 87 int gpc, ppc, i; local 89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; 92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][pp [all...] |
H A D | ctxgp100.c | 52 int gpc, ppc, n = 0; local 58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 60 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 63 const u32 o = PPC_UNIT(gpc, ppc, 0); 65 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 74 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 97 int gpc; local 99 for (gpc 114 const u8 gpc = gr->sm[sm].gpc; local [all...] |
H A D | gf117.c | 131 u8 bank[GPC_MAX] = {}, gpc, i, j; local 142 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 144 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); 145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 147 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
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H A D | ctxtu102.c | 34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 38 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); 40 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); 41 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
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H A D | ctxga102.c | 25 ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 29 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc); 31 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
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H A D | ctxgf117.c | 254 int gpc, ppc; local 259 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 261 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; 262 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; 264 const u32 o = PPC_UNIT(gpc, ppc, 0); 266 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 270 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 272 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][pp [all...] |
H A D | tu102.c | 45 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc); 47 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm); 60 u8 bank[GPC_MAX] = {}, gpc, i, j; local 71 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 72 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 73 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); 74 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 76 nvkm_wr32(device, GPC_UNIT(gpc, [all...] |
H A D | ctxgv100.c | 73 int gpc, ppc, n = 0; local 79 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 81 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 85 const u32 o = PPC_UNIT(gpc, ppc, 0); 87 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 96 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 160 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 164 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tp [all...] |
H A D | gp102.c | 89 u32 mask = 0, data, gpc; local 91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; 93 mask |= data << (gpc * 4);
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H A D | gf100.c | 1234 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) argument 1241 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 1242 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 1243 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 1244 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 1250 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 1252 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1295 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) argument 1299 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 1300 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tp 1316 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) argument 1361 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) argument 1415 int rop, gpc; local 1558 u32 gpc; local 1897 int tpc, gpc; local 2172 int gpc, i, j; local 2215 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 2223 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc) argument 2240 int gpc, tpc; local 2292 u8 bank[GPC_MAX] = {}, gpc, i, j; local 2345 int gpc, tpc; local [all...] |
H A D | ctxgf100.c | 1037 int gpc, tpc; local 1042 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1043 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1044 const u32 o = TPC_UNIT(gpc, tpc, 0x0520); 1084 data |= gr->sm[sm++].gpc << (j * 8); 1253 int i, gpc; local 1265 for (gpc = 0; atarget && gpc < g 1285 gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc) argument 1293 gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument [all...] |
H A D | gp100.c | 72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); 76 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
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H A D | gk104.c | 418 int gpc, ppc; local 420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 422 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
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H A D | gf100.h | 127 u8 gpc; member in struct:gf100_gr::__anon243 175 void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc); 176 void (*init_504430)(struct gf100_gr *, int gpc, int tpc); 177 void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc); 182 void (*trap_mp)(struct gf100_gr *, int gpc, int tpc); 263 u32 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc);
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H A D | gm107.c | 294 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) argument 297 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); 298 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); 302 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) argument 305 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
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H A D | ctxgm107.c | 909 int gpc, ppc, n = 0; local 914 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 916 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 917 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; 919 const u32 o = PPC_UNIT(gpc, ppc, 0); 921 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 926 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 929 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][pp 950 gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument [all...] |
/linux-master/drivers/pmdomain/imx/ |
H A D | Makefile | 2 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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/linux-master/drivers/gpu/drm/nouveau/include/nvif/ |
H A D | ifc00d.h | 37 __u8 gpc; member in struct:gp100_vmm_fault_cancel_v0
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/linux-master/arch/arm/mach-imx/ |
H A D | cpu-imx5.c | 130 u32 gpc; local 152 gpc = readl_relaxed(tigerp_base + ARM_GPC); 153 gpc |= DBGEN; 154 writel_relaxed(gpc, tigerp_base + ARM_GPC);
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/linux-master/arch/arm/mach-s3c/ |
H A D | gpio-core.h | 81 static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) argument 83 return container_of(gpc, struct samsung_gpio_chip, chip);
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/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
H A D | fault.h | 30 u8 gpc; member in struct:nvkm_fault_data
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/linux-master/arch/x86/kvm/ |
H A D | xen.c | 40 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; local 48 read_lock_irq(&gpc->lock); 49 while (!kvm_gpc_check(gpc, PAGE_SIZE)) { 50 read_unlock_irq(&gpc->lock); 52 ret = kvm_gpc_refresh(gpc, PAGE_SIZE); 56 read_lock_irq(&gpc->lock); 76 struct shared_info *shinfo = gpc->khva; 83 struct compat_shared_info *shinfo = gpc->khva; 99 read_unlock_irq(&gpc->lock); 594 struct gfn_to_pfn_cache *gpc local 651 struct gfn_to_pfn_cache *gpc = &v->arch.xen.vcpu_info_cache; local 1383 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; local 1740 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; local 1880 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; local [all...] |