engine/gr/ctxgf100.c

1037 	int gpc, tpc;
1042 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1043 		for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1044 			const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
1084 				data |= gr->sm[sm++].gpc << (j * 8);
1253 	int i, gpc;
1265 			for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) {
1266 				if (abits[gpc] < gr->tpc_nr[gpc]) {
1267 					abits[gpc]++;
1273 		for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1274 			u32 bbits = gr->tpc_nr[gpc] - abits[gpc];
1275 			amask |= ((1 << abits[gpc]) - 1) << (gpc * 8);
1276 			bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8);
1285 gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc)
1288 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
1289 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
1293 gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
1296 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm);
1297 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), sm);
1298 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
1299 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
1309 		func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm);
1311 			func->tpc_nr(gr, gr->sm[sm].gpc);