Searched refs:fb_div (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c78 * @fb_div: resulting feedback divider
87 unsigned int *fb_div, unsigned int *ref_div)
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
101 if (*fb_div > fb_div_max) {
102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
103 *fb_div = fb_div_max;
134 unsigned fb_div_min, fb_div_max, fb_div; local
211 ref_div_max, &fb_div, &ref_div);
212 diff = abs(target_clock - (pll->reference_freq * fb_div) /
226 &fb_div,
84 amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom, unsigned int den, unsigned int post_div, unsigned int fb_div_max, unsigned int ref_div_max, unsigned int *fb_div, unsigned int *ref_div) argument
[all...]
H A Datombios_crtc.h49 u32 fb_div,
H A Damdgpu_atombios.h41 u32 fb_div; member in union:atom_clock_dividers::__anon286
66 u32 fb_div; member in union:atom_mpll_param::__anon288
H A Datombios_crtc.c582 u32 fb_div,
609 args.v1.usFbDiv = cpu_to_le16(fb_div);
619 args.v2.usFbDiv = cpu_to_le16(fb_div);
629 args.v3.usFbDiv = cpu_to_le16(fb_div);
646 args.v5.usFbDiv = cpu_to_le16(fb_div);
676 args.v6.usFbDiv = cpu_to_le16(fb_div);
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
854 &fb_div, &frac_fb_div, &ref_div, &post_div);
861 ref_div, fb_div, frac_fb_div, post_div,
867 u32 amount = (((fb_div * 1
575 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument
[all...]
H A Dsi.c1731 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; local
1734 do_div(fb_div, ref_freq);
1737 if (fb_div > fb_mask)
1740 fb_div &= fb_mask;
1759 *optimal_fb_div = fb_div;
1777 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local
1795 &fb_div, &vclk_div, &dclk_div);
1824 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
1829 if (fb_div < 307200)
1900 unsigned fb_div local
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/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; local
45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
46 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
47 fb_div <<= 1;
48 fb_div *= spll->reference_freq;
56 sclk = fb_div / ref_div;
73 uint32_t fb_div, ref_div, post_div, mclk; local
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
76 fb_div
351 calc_eng_mem_clock(struct radeon_device *rdev, uint32_t req_clock, int *fb_div, int *post_div) argument
394 int fb_div, post_div; local
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H A Drs780_dpm.c88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) argument
414 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
416 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
459 rs780_force_fbdiv(rdev, max_dividers.fb_div);
461 if (max_dividers.fb_div > min_dividers.fb_div) {
463 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
464 MAX_FEEDBACK_DIV(max_dividers.fb_div),
1048 rs780_force_fbdiv(rdev, dividers.fb_div);
[all...]
H A Dradeon_display.c924 * @fb_div: resulting feedback divider
932 unsigned *fb_div, unsigned *ref_div)
939 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
942 if (*fb_div > fb_div_max) {
943 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
944 *fb_div = fb_div_max;
973 unsigned fb_div_min, fb_div_max, fb_div; local
1053 ref_div_max, &fb_div, &ref_div);
1054 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1068 &fb_div,
930 avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument
[all...]
H A Dradeon_uvd.c967 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; local
970 do_div(fb_div, ref_freq);
973 if (fb_div > fb_mask)
976 fb_div &= fb_mask;
995 *optimal_fb_div = fb_div;
H A Datombios_crtc.c822 u32 fb_div,
849 args.v1.usFbDiv = cpu_to_le16(fb_div);
859 args.v2.usFbDiv = cpu_to_le16(fb_div);
869 args.v3.usFbDiv = cpu_to_le16(fb_div);
886 args.v5.usFbDiv = cpu_to_le16(fb_div);
915 args.v6.usFbDiv = cpu_to_le16(fb_div);
1062 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1094 &fb_div, &frac_fb_div, &ref_div, &post_div);
1097 &fb_div, &frac_fb_div, &ref_div, &post_div);
1100 &fb_div,
815 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
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H A Drv730_dpm.c157 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
171 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
H A Dradeon_legacy_crtc.c267 uint16_t fb_div)
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
266 radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, uint16_t fb_div) argument
H A Dradeon_mode.h555 u32 fb_div; member in union:atom_clock_dividers::__anon508
580 u32 fb_div; member in union:atom_mpll_param::__anon510
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local
76 &fb_div, &vclk_div, &dclk_div);
80 fb_div |= 1;
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
H A Dni_dpm.c2096 u32 fb_div; local
2117 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2121 fb_div &= ~0x00001FFF;
2122 fb_div >>= 1;
2131 if (fb_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2140 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
H A Dsi.c6977 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local
6995 &fb_div, &vclk_div, &dclk_div);
7024 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7029 if (fb_div < 307200)
7462 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; local
7483 &fb_div, &evclk_div, &ecclk_div);
7515 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
H A Dr600.c204 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local
233 &fb_div, &vclk_div, &dclk_div);
238 fb_div >>= 1;
240 fb_div |= 1;
256 UPLL_FB_DIV(fb_div) |
H A Drv6xx_dpm.c529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
607 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
H A Dsi_dpm.c2787 u32 fb_div, p_div; local
2807 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2811 fb_div &= ~0x00001FFF;
2812 fb_div >>= 1;
2817 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2827 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
H A Dradeon_atombios.c2862 dividers->fb_div = args.v1.ucFbDiv;
2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2883 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
H A Devergreen.c1192 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local
1211 &fb_div, &vclk_div, &dclk_div);
1238 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
1243 if (fb_div < 307200)
H A Dci_dpm.c3137 fbdiv = dividers.fb_div & 0x3FFFFFF;
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c654 struct fixed31_32 fb_div; local
674 fb_div = dc_fixpt_from_fraction(
676 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
682 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
/linux-master/drivers/video/fbdev/aty/
H A Dradeon_base.c1539 int fb_div, pll_output_freq = 0; local
1628 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1631 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1634 pr_debug("fb_div = 0x%x\n", fb_div);
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2947 u32 fb_div, p_div; local
2966 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2970 fb_div &= ~0x00001FFF;
2971 fb_div >>= 1;
2976 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2986 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |

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