/linux-master/tools/power/cpupower/utils/idle_monitor/ |
H A D | amd_fam14h_idle.c | 98 unsigned int *enable_bit, 103 *enable_bit = PCI_NON_PC0_ENABLE_BIT; 107 *enable_bit = PCI_PC1_ENABLE_BIT; 111 *enable_bit = PCI_PC6_ENABLE_BIT; 115 *enable_bit = PCI_NBP1_ENTERED_BIT; 126 int enable_bit, pci_offset, ret; local 129 ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); 136 val |= 1 << enable_bit; 145 val |= 1 << enable_bit; 148 dprint("Init %s: offset: 0x%x enable_bit 96 amd_fam14h_get_pci_info(struct cstate *state, unsigned int *pci_offset, unsigned int *enable_bit, unsigned int cpu) argument 161 int enable_bit, pci_offset, ret; local [all...] |
/linux-master/drivers/clk/ti/ |
H A D | clkt_dflt.c | 146 *other_bit = clk->enable_bit; 172 *idlest_bit = clk->enable_bit; 222 v &= ~(1 << clk->enable_bit); 224 v |= (1 << clk->enable_bit); 252 v |= (1 << clk->enable_bit); 254 v &= ~(1 << clk->enable_bit); 279 v ^= BIT(clk->enable_bit); 281 v &= BIT(clk->enable_bit);
|
H A D | clkt_iclk.c | 37 v |= (1 << clk->enable_bit); 52 v &= ~(1 << clk->enable_bit); 75 *idlest_bit = clk->enable_bit;
|
H A D | interface.c | 44 clk_hw->enable_bit = bit_idx; 67 u8 enable_bit = 0; local 73 enable_bit = reg.bit; 83 enable_bit, ops);
|
H A D | gate.c | 108 clk_hw->enable_bit = bit_idx; 134 u8 enable_bit = 0; local 142 enable_bit = reg.bit; 160 enable_bit, clk_gate_flags, ops, hw_ops); 179 gate->enable_bit = gate->enable_reg.bit;
|
H A D | clk-3xxx.c | 153 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; 176 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) 177 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; 179 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
|
H A D | clkctrl.c | 148 if (!clk->enable_bit) 154 val |= clk->enable_bit; 178 if (!clk->enable_bit) 211 if (val & clk->enable_bit) 344 clk_hw->enable_bit = data->bit; 663 hw->enable_bit = MODULEMODE_SWCTRL; 665 hw->enable_bit = MODULEMODE_HWCTRL;
|
/linux-master/drivers/regulator/ |
H A D | mc13xxx.h | 16 int enable_bit; member in struct:mc13xxx_regulator 67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
|
H A D | tps6586x-regulator.c | 59 int enable_bit[2]; member in struct:tps6586x_regulator 128 .enable_bit[0] = (ebit0), \ 130 .enable_bit[1] = (ebit1), 153 .enable_bit[0] = (ebit0), \ 155 .enable_bit[1] = (ebit1), 274 ri->enable_bit[0] == ri->enable_bit[1]) 285 if (!(val2 & (1 << ri->enable_bit[1]))) 292 if (!(val1 & (1 << ri->enable_bit[0]))) { 294 1 << ri->enable_bit[ [all...] |
H A D | mc13xxx-regulator-core.c | 36 mc13xxx_regulators[id].enable_bit, 37 mc13xxx_regulators[id].enable_bit); 49 mc13xxx_regulators[id].enable_bit, 0); 63 return (val & mc13xxx_regulators[id].enable_bit) != 0;
|
H A D | mc13783-regulator.c | 330 u32 en_val = mc13xxx_regulators[id].enable_bit; 339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, 355 dis_val = mc13xxx_regulators[id].enable_bit; 357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, 380 return (val & mc13xxx_regulators[id].enable_bit) != 0;
|
/linux-master/arch/arm/mach-omap1/ |
H A D | clock_data.c | 43 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ 50 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ 56 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ 100 .enable_bit = EN_CKOUT_ARM, 110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, 131 .enable_bit = EN_PERCK, 148 .enable_bit = EN_GPIOCK, 158 .enable_bit = EN_XORPCK, 170 .enable_bit = EN_TIMCK, 181 .enable_bit [all...] |
H A D | clock.c | 50 return val & 1 << clk->enable_bit ? 48000000 : 12000000; 198 ret = regval32 & (1 << clk->enable_bit); 388 val = 1 << clk->enable_bit; 395 val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); 554 regval32 |= (1 << clk->enable_bit); 558 regval16 |= (1 << clk->enable_bit); 599 regval32 &= ~(1 << clk->enable_bit); 603 regval16 &= ~(1 << clk->enable_bit);
|
/linux-master/drivers/clk/renesas/ |
H A D | clk-sh73a0.c | 91 u32 enable_bit = name[3] - '0'; local 94 switch (enable_bit) { 110 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { 113 if (enable_bit == 1 || enable_bit == 2)
|
/linux-master/drivers/clk/ |
H A D | clk-max9485.c | 73 u8 enable_bit; member in struct:max9485_clk_hw 115 clk_hw->enable_bit, 116 clk_hw->enable_bit); 123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); 206 u8 enable_bit; member in struct:max9485_clk 213 .enable_bit = MAX9485_MCLK_ENABLE, 231 .enable_bit = MAX9485_CLKOUT1_ENABLE, 240 .enable_bit = MAX9485_CLKOUT2_ENABLE, 321 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; [all...] |
/linux-master/include/uapi/linux/ |
H A D | user_events.h | 44 __u8 enable_bit; member in struct:user_reg
|
/linux-master/include/linux/ |
H A D | sh_clk.h | 57 unsigned int enable_bit; member in struct:clk 121 .enable_bit = _enable_bit, \ 155 .enable_bit = _shift, \ 179 .enable_bit = 0, /* unused */ \ 192 .enable_bit = 0, /* unused */ \
|
/linux-master/tools/testing/selftests/user_events/ |
H A D | ftrace_test.c | 178 reg.enable_bit = 31; 243 reg.enable_bit = 31; 260 reg.enable_bit = 30; 265 reg.enable_bit = 29; 277 ASSERT_EQ(1 << reg.enable_bit, self->check); 306 reg.enable_bit = 31; 342 ASSERT_NE(1 << reg.enable_bit, self->check); 363 reg.enable_bit = 31; 380 ASSERT_EQ(1 << reg.enable_bit, self->check); 397 reg.enable_bit [all...] |
H A D | perf_test.c | 144 reg.enable_bit = 31; 174 ASSERT_EQ(1 << reg.enable_bit, self->check); 208 reg.enable_bit = 31; 236 ASSERT_EQ(1 << reg.enable_bit, self->check);
|
/linux-master/drivers/thermal/intel/int340x_thermal/ |
H A D | processor_thermal_mbox.c | 117 int enable_bit, int time_window) 143 data |= BIT(enable_bit); 145 data &= ~BIT(enable_bit); 116 processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable, int enable_bit, int time_window) argument
|
/linux-master/samples/user_events/ |
H A D | example.c | 26 reg.enable_bit = 31;
|
/linux-master/drivers/xen/xen-pciback/ |
H A D | conf_space_capability.c | 193 u16 enable_bit; /* bit for enabling MSI/MSI-X */ member in struct:msi_msix_field_config 197 .enable_bit = PCI_MSI_FLAGS_ENABLE, 201 .enable_bit = PCI_MSIX_FLAGS_ENABLE, 238 if (new_value & field_config->enable_bit) {
|
/linux-master/drivers/sh/clk/ |
H A D | cpg.c | 41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); 56 (read(mapped_status) & (1 << clk->enable_bit)) && i; 61 clk->enable_reg, clk->enable_bit); 70 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); 123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; 139 value &= ~(clk->div_mask << clk->enable_bit); 140 value |= (idx << clk->enable_bit);
|
/linux-master/drivers/clk/ingenic/ |
H A D | x1830-cgu.c | 130 .enable_bit = 0, 153 .enable_bit = 0, 176 .enable_bit = 0, 199 .enable_bit = 0,
|
H A D | cgu.h | 45 * @enable_bit: the index of the enable bit in the PLL control register, or 61 s8 enable_bit; member in struct:ingenic_cgu_pll_info
|