Searched refs:dpp_inst (Results 1 - 25 of 29) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.h31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
H A Ddcn302_hwseq.c45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
55 switch (dpp_inst) {
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
93 DPPCLK_DTO_ENABLE[dpp_inst], 1);
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_hwseq.h32 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
H A Ddcn303_hwseq.c46 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
68 DPPCLK_DTO_ENABLE[dpp_inst], 1);
71 DPPCLK_DTO_ENABLE[dpp_inst], 0);
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
H A Ddcn20_dccg.h404 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.h46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
H A Ddcn314_hwseq.c381 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) argument
388 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.c45 uint32_t dpp_inst, uint32_t enable)
49 switch (dpp_inst) {
68 static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, argument
73 if (dccg->dpp_clock_gated[dpp_inst]) {
93 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
97 dcn35_set_dppclk_enable(dccg, dpp_inst, true);
99 dcn35_set_dppclk_enable(dccg, dpp_inst, false);
100 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
484 unsigned int dpp_inst,
489 if (dccg->dpp_clock_gated[dpp_inst]
44 dcn35_set_dppclk_enable(struct dccg *dccg, uint32_t dpp_inst, uint32_t enable) argument
482 dccg35_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.c330 unsigned int dpp_inst,
335 if (dccg->dpp_clock_gated[dpp_inst] != clock_on)
340 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
341 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
346 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1);
347 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
352 dccg->dpp_clock_gated[dpp_inst] = !clock_on;
328 dccg314_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) argument
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h96 int dpp_inst,
185 unsigned int dpp_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dccg.c47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, argument
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h121 unsigned int dpp_inst,
124 unsigned int dpp_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.h38 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
50 if (dccg->dpp_clock_gated[dpp_inst]) {
71 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
75 DPPCLK_DTO_ENABLE[dpp_inst], 1);
78 DPPCLK_DTO_ENABLE[dpp_inst], 0);
80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
H A Ddcn31_dccg.h199 int dpp_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h104 unsigned int dpp_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_replay.c175 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
177 copy_settings_data->dpp_inst = 0;
H A Ddmub_psr.c342 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
344 copy_settings_data->dpp_inst = 0;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
116 dpp_inst = i;
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.h92 unsigned int dpp_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];
126 clk_mgr->dccg, dpp_inst, dppclk_khz);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c186 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
191 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
209 clk_mgr->dccg, dpp_inst, dppclk_khz);
210 dppclk_active[dpp_inst] = true;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c319 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
324 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
342 clk_mgr->dccg, dpp_inst, dppclk_khz);

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