Searched refs:dpcd (Results 1 - 25 of 50) sorted by relevance

12

/linux-master/include/drm/display/
H A Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
103 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
108 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
110 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
114 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
116 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
120 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZ argument
127 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
134 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
141 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
148 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
155 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
162 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
219 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
225 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
233 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
[all...]
/linux-master/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument
300 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
326 rd_interval = dpcd[offset];
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true);
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false);
374 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
376 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
380 if (dpcd[DP_DPCD_RE
373 drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
397 drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
804 drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 type) argument
821 drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument
908 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
918 drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
972 drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
1006 drm_dp_read_downstream_info(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) argument
1050 drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
1079 drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument
1144 drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument
1187 drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument
1243 drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
1274 drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
1305 drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 color_spc) argument
1338 drm_dp_downstream_mode(struct drm_device *dev, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
1404 drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid, struct drm_dp_aux *aux) argument
1492 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
1547 drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 port_cap[4]) argument
1574 drm_dp_read_sink_count_cap(struct drm_connector *connector, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const struct drm_dp_desc *desc) argument
2533 drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, u8 *buf, int buf_size) argument
2569 drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) argument
2590 drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, u8 caps[DP_LTTPR_PHY_CAP_SIZE]) argument
2958 drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
3056 drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c42 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc);
69 u8 *dpcd = outp->dp.dpcd; local
78 !drm_dp_read_dpcd_caps(aux, dpcd) &&
79 !drm_dp_read_lttpr_common_caps(aux, dpcd, outp->dp.lttpr.caps)) {
99 ret = drm_dp_read_dpcd_caps(aux, dpcd);
103 outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && dpcd[DP_DPCD_REV] >= 0x13) {
134 outp->dp.rate[j].dpcd = i;
143 u32 max_rate = dpcd[DP_MAX_LINK_RAT
225 u8 *dpcd = nv_encoder->dp.dpcd; local
[all...]
H A Dnouveau_encoder.h84 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:nouveau_encoder::__anon760::__anon762
/linux-master/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:anx6345
99 u8 dp_bw, dpcd[2]; local
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE);
150 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) {
151 err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]);
158 dpcd[0] &= ~DP_SET_POWER_MASK;
159 dpcd[0] |= DP_SET_POWER_D0;
161 err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]);
182 if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
201 if (drm_dp_enhanced_frame_cap(anx6345->dpcd))
[all...]
H A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:anx78xx
606 u8 dp_bw, dpcd[2]; local
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) {
664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);
671 dpcd[0] &= ~DP_SET_POWER_MASK;
672 dpcd[0] |= DP_SET_POWER_D0;
674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);
695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE],
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
362 dig_connector->dpcd);
369 dig_connector->dpcd[0] = 0;
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
252 amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector, const u8 dpcd[DP_DPCD_SIZE], unsigned pix_clock, unsigned *dp_lanes, unsigned *dp_rate) argument
495 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:amdgpu_atombios_dp_link_train_info
[all...]
/linux-master/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c35 if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
53 u8 *dpcd, major, minor; local
56 dpcd = dp_panel->dpcd;
57 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd);
61 dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd);
63 link_info->revision = dpcd[DP_DPCD_REV];
67 link_info->rate = drm_dp_max_link_rate(dpcd);
68 link_info->num_lanes = drm_dp_max_lane_count(dpcd);
82 if (drm_dp_enhanced_frame_cap(dpcd))
[all...]
H A Ddp_panel.h38 /* dpcd raw data */
39 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:dp_panel
H A Ddp_ctrl.c140 const u8 *dpcd = ctrl->panel->dpcd; local
149 if (drm_dp_alternate_scrambler_reset_cap(dpcd))
161 if (drm_dp_enhanced_frame_cap(dpcd))
1141 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1219 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1235 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1238 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1253 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1278 const u8 *dpcd local
1446 const u8 *dpcd = ctrl->panel->dpcd; local
1571 const u8 *dpcd = ctrl->panel->dpcd; local
[all...]
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.h14 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
H A Dintel_dp_link_training.c68 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
73 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
84 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
88 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
117 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
122 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
160 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
165 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
181 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
216 u8 dpcd[DP_RECEIVER_CAP_SIZ local
67 intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy) argument
83 intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument
[all...]
H A Dintel_dp.c163 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
171 return drm_dp_max_lane_count(intel_dp->dpcd);
180 /* update sink rates from dpcd */
217 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
964 if (!drm_dp_is_branch(intel_dp->dpcd))
981 if (!drm_dp_is_branch(intel_dp->dpcd))
1019 (!drm_dp_is_branch(intel_dp->dpcd) ||
2928 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3038 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3039 drm_dp_is_branch(intel_dp->dpcd)
5361 u8 *dpcd = intel_dp->dpcd; local
6124 u8 dpcd[DP_RECEIVER_CAP_SIZE]; local
[all...]
/linux-master/drivers/gpu/drm/tegra/
H A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
182 link->revision = dpcd[DP_DPCD_REV];
183 link->max_rate = drm_dp_max_link_rate(dpcd);
184 link->max_lanes = drm_dp_max_lane_count(dpcd);
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
[all...]
/linux-master/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h102 int dpcd; /* -1 for non-indexed rates */ member in struct:nvif_outp_dp_rate
107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h228 __s8 dpcd; member in struct:nvif_outp_dp_rates_args::nvif_outp_dp_rates_v0::__anon740
243 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:nvif_outp_dp_train_args::nvif_outp_dp_train_v0
/linux-master/drivers/gpu/drm/radeon/
H A Datombios_dp.c307 const u8 dpcd[DP_DPCD_SIZE],
313 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
314 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
375 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
396 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
398 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
399 dig_connector->dpcd);
406 dig_connector->dpcd[0] = 0;
463 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
490 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
306 radeon_dp_get_dp_link_config(struct drm_connector *connector, const u8 dpcd[DP_DPCD_SIZE], unsigned pix_clock, unsigned *dp_lanes, unsigned *dp_rate) argument
545 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:radeon_dp_link_train_info
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c242 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 &&
243 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)
246 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 &&
247 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
252 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
284 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater)
285 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
318 .pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED,
327 sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0;
338 if (outp->dp.rate[rate].dpcd >
[all...]
H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:nvkm_outp::__anon779::__anon781
51 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member in struct:nvkm_outp::__anon779::__anon781::__anon782
/linux-master/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.h103 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:cdn_dp_device
/linux-master/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c263 uint8_t dpcd[4]; member in struct:cdv_intel_dp
326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
342 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvif/
H A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, argument
126 memcpy(args.dpcd, dpcd, sizeof(args.dpcd));
148 args.rate[i].dpcd = rate->dpcd;
/linux-master/drivers/gpu/drm/i915/gvt/
H A Ddisplay.h166 struct intel_vgpu_dpcd_data *dpcd; member in struct:intel_vgpu_port
H A Ddisplay.c519 kfree(port->dpcd);
520 port->dpcd = NULL;
552 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
553 if (!port->dpcd) {
562 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
563 port->dpcd->data_valid = true;
564 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c292 * @dpcd: DP configuration data from currently connected sink device
315 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:zynqmp_dp
703 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
751 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
752 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
768 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
802 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
808 if (dp->dpcd[3] & 0x1) {
1540 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1541 sizeof(dp->dpcd));
[all...]

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