1/* 2 * Copyright �� 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23#ifndef _DRM_DP_HELPER_H_ 24#define _DRM_DP_HELPER_H_ 25 26#include <linux/delay.h> 27#include <linux/i2c.h> 28 29#include <drm/display/drm_dp.h> 30#include <drm/drm_connector.h> 31 32struct drm_device; 33struct drm_dp_aux; 34struct drm_panel; 35 36bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 41 int lane); 42u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane); 44u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 45 int lane); 46 47int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy, bool uhbr); 49int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 50 enum drm_dp_phy dp_phy, bool uhbr); 51 52void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 54void drm_dp_lttpr_link_train_clock_recovery_delay(void); 55void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 57void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 59 60int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 61bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane_count); 63bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane_count); 65bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 66bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 69u8 drm_dp_link_rate_to_bw_code(int link_rate); 70int drm_dp_bw_code_to_link_rate(u8 link_bw); 71 72const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 73 74/** 75 * struct drm_dp_vsc_sdp - drm DP VSC SDP 76 * 77 * This structure represents a DP VSC SDP of drm 78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 79 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 80 * 81 * @sdp_type: secondary-data packet type 82 * @revision: revision number 83 * @length: number of valid data bytes 84 * @pixelformat: pixel encoding format 85 * @colorimetry: colorimetry format 86 * @bpc: bit per color 87 * @dynamic_range: dynamic range information 88 * @content_type: CTA-861-G defines content types and expected processing by a sink device 89 */ 90struct drm_dp_vsc_sdp { 91 unsigned char sdp_type; 92 unsigned char revision; 93 unsigned char length; 94 enum dp_pixelformat pixelformat; 95 enum dp_colorimetry colorimetry; 96 int bpc; 97 enum dp_dynamic_range dynamic_range; 98 enum dp_content_type content_type; 99}; 100 101void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 102 103bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 104 105int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 106 107static inline int 108drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 109{ 110 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 111} 112 113static inline u8 114drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 115{ 116 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 117} 118 119static inline bool 120drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 121{ 122 return dpcd[DP_DPCD_REV] >= 0x11 && 123 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 124} 125 126static inline bool 127drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 128{ 129 return dpcd[DP_DPCD_REV] >= 0x11 && 130 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 131} 132 133static inline bool 134drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 135{ 136 return dpcd[DP_DPCD_REV] >= 0x12 && 137 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 138} 139 140static inline bool 141drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 142{ 143 return dpcd[DP_DPCD_REV] >= 0x11 || 144 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 145} 146 147static inline bool 148drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 149{ 150 return dpcd[DP_DPCD_REV] >= 0x14 && 151 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 152} 153 154static inline u8 155drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 156{ 157 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 158 DP_TRAINING_PATTERN_MASK; 159} 160 161static inline bool 162drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 163{ 164 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 165} 166 167/* DP/eDP DSC support */ 168u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 169u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 170 bool is_edp); 171u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 172int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 173 u8 dsc_bpc[3]); 174 175static inline bool 176drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 177{ 178 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 179 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 180} 181 182static inline u16 183drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 184{ 185 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 186 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 187 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 188} 189 190static inline u32 191drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 192{ 193 /* Max Slicewidth = Number of Pixels * 320 */ 194 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 195 DP_DSC_SLICE_WIDTH_MULTIPLIER; 196} 197 198/** 199 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 200 * @dsc_dpcd : DSC-capability DPCDs of the sink 201 * @output_format: output_format which is to be checked 202 * 203 * Returns true if the sink supports DSC with the given output_format, false otherwise. 204 */ 205static inline bool 206drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 207{ 208 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 209} 210 211/* Forward Error Correction Support on DP 1.4 */ 212static inline bool 213drm_dp_sink_supports_fec(const u8 fec_capable) 214{ 215 return fec_capable & DP_FEC_CAPABLE; 216} 217 218static inline bool 219drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 220{ 221 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 222} 223 224static inline bool 225drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 226{ 227 return dpcd[DP_EDP_CONFIGURATION_CAP] & 228 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 229} 230 231/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 232static inline bool 233drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 234{ 235 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 236 DP_MSA_TIMING_PAR_IGNORED; 237} 238 239/** 240 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 241 * @edp_dpcd: The DPCD to check 242 * 243 * Note that currently this function will return %false for panels which support various DPCD 244 * backlight features but which require the brightness be set through PWM, and don't support setting 245 * the brightness level via the DPCD. 246 * 247 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 248 * otherwise 249 */ 250static inline bool 251drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 252{ 253 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 254} 255 256/** 257 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 258 * @link_rate: link rate in 10kbits/s units 259 * 260 * Determine if the provided link rate is an UHBR rate. 261 * 262 * Returns: %True if @link_rate is an UHBR rate. 263 */ 264static inline bool drm_dp_is_uhbr_rate(int link_rate) 265{ 266 return link_rate >= 1000000; 267} 268 269/* 270 * DisplayPort AUX channel 271 */ 272 273/** 274 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 275 * @address: address of the (first) register to access 276 * @request: contains the type of transaction (see DP_AUX_* macros) 277 * @reply: upon completion, contains the reply type of the transaction 278 * @buffer: pointer to a transmission or reception buffer 279 * @size: size of @buffer 280 */ 281struct drm_dp_aux_msg { 282 unsigned int address; 283 u8 request; 284 u8 reply; 285 void *buffer; 286 size_t size; 287}; 288 289struct cec_adapter; 290struct drm_connector; 291struct drm_edid; 292 293/** 294 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 295 * @lock: mutex protecting this struct 296 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 297 * @connector: the connector this CEC adapter is associated with 298 * @unregister_work: unregister the CEC adapter 299 */ 300struct drm_dp_aux_cec { 301 struct mutex lock; 302 struct cec_adapter *adap; 303 struct drm_connector *connector; 304 struct delayed_work unregister_work; 305}; 306 307/** 308 * struct drm_dp_aux - DisplayPort AUX channel 309 * 310 * An AUX channel can also be used to transport I2C messages to a sink. A 311 * typical application of that is to access an EDID that's present in the sink 312 * device. The @transfer() function can also be used to execute such 313 * transactions. The drm_dp_aux_register() function registers an I2C adapter 314 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 315 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 316 * transfers by default; if a partial response is received, the adapter will 317 * drop down to the size given by the partial response for this transaction 318 * only. 319 */ 320struct drm_dp_aux { 321 /** 322 * @name: user-visible name of this AUX channel and the 323 * I2C-over-AUX adapter. 324 * 325 * It's also used to specify the name of the I2C adapter. If set 326 * to %NULL, dev_name() of @dev will be used. 327 */ 328 const char *name; 329 330 /** 331 * @ddc: I2C adapter that can be used for I2C-over-AUX 332 * communication 333 */ 334 struct i2c_adapter ddc; 335 336 /** 337 * @dev: pointer to struct device that is the parent for this 338 * AUX channel. 339 */ 340 struct device *dev; 341 342 /** 343 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 344 * Beware, this may be %NULL before drm_dp_aux_register() has been 345 * called. 346 * 347 * It should be set to the &drm_device that will be using this AUX 348 * channel as early as possible. For many graphics drivers this should 349 * happen before drm_dp_aux_init(), however it's perfectly fine to set 350 * this field later so long as it's assigned before calling 351 * drm_dp_aux_register(). 352 */ 353 struct drm_device *drm_dev; 354 355 /** 356 * @crtc: backpointer to the crtc that is currently using this 357 * AUX channel 358 */ 359 struct drm_crtc *crtc; 360 361 /** 362 * @hw_mutex: internal mutex used for locking transfers. 363 * 364 * Note that if the underlying hardware is shared among multiple 365 * channels, the driver needs to do additional locking to 366 * prevent concurrent access. 367 */ 368 struct mutex hw_mutex; 369 370 /** 371 * @crc_work: worker that captures CRCs for each frame 372 */ 373 struct work_struct crc_work; 374 375 /** 376 * @crc_count: counter of captured frame CRCs 377 */ 378 u8 crc_count; 379 380 /** 381 * @transfer: transfers a message representing a single AUX 382 * transaction. 383 * 384 * This is a hardware-specific implementation of how 385 * transactions are executed that the drivers must provide. 386 * 387 * A pointer to a &drm_dp_aux_msg structure describing the 388 * transaction is passed into this function. Upon success, the 389 * implementation should return the number of payload bytes that 390 * were transferred, or a negative error-code on failure. 391 * 392 * Helpers will propagate these errors, with the exception of 393 * the %-EBUSY error, which causes a transaction to be retried. 394 * On a short, helpers will return %-EPROTO to make it simpler 395 * to check for failure. 396 * 397 * The @transfer() function must only modify the reply field of 398 * the &drm_dp_aux_msg structure. The retry logic and i2c 399 * helpers assume this is the case. 400 * 401 * Also note that this callback can be called no matter the 402 * state @dev is in and also no matter what state the panel is 403 * in. It's expected: 404 * 405 * - If the @dev providing the AUX bus is currently unpowered then 406 * it will power itself up for the transfer. 407 * 408 * - If we're on eDP (using a drm_panel) and the panel is not in a 409 * state where it can respond (it's not powered or it's in a 410 * low power state) then this function may return an error, but 411 * not crash. It's up to the caller of this code to make sure that 412 * the panel is powered on if getting an error back is not OK. If a 413 * drm_panel driver is initiating a DP AUX transfer it may power 414 * itself up however it wants. All other code should ensure that 415 * the pre_enable() bridge chain (which eventually calls the 416 * drm_panel prepare function) has powered the panel. 417 */ 418 ssize_t (*transfer)(struct drm_dp_aux *aux, 419 struct drm_dp_aux_msg *msg); 420 421 /** 422 * @wait_hpd_asserted: wait for HPD to be asserted 423 * 424 * This is mainly useful for eDP panels drivers to wait for an eDP 425 * panel to finish powering on. This is an optional function. 426 * 427 * This function will efficiently wait for the HPD signal to be 428 * asserted. The `wait_us` parameter that is passed in says that we 429 * know that the HPD signal is expected to be asserted within `wait_us` 430 * microseconds. This function could wait for longer than `wait_us` if 431 * the logic in the DP controller has a long debouncing time. The 432 * important thing is that if this function returns success that the 433 * DP controller is ready to send AUX transactions. 434 * 435 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 436 * expired and HPD wasn't asserted. This function should not print 437 * timeout errors to the log. 438 * 439 * The semantics of this function are designed to match the 440 * readx_poll_timeout() function. That means a `wait_us` of 0 means 441 * to wait forever. Like readx_poll_timeout(), this function may sleep. 442 * 443 * NOTE: this function specifically reports the state of the HPD pin 444 * that's associated with the DP AUX channel. This is different from 445 * the HPD concept in much of the rest of DRM which is more about 446 * physical presence of a display. For eDP, for instance, a display is 447 * assumed always present even if the HPD pin is deasserted. 448 */ 449 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 450 451 /** 452 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 453 */ 454 unsigned i2c_nack_count; 455 /** 456 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 457 */ 458 unsigned i2c_defer_count; 459 /** 460 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 461 */ 462 struct drm_dp_aux_cec cec; 463 /** 464 * @is_remote: Is this AUX CH actually using sideband messaging. 465 */ 466 bool is_remote; 467 468 /** 469 * @powered_down: If true then the remote endpoint is powered down. 470 */ 471 bool powered_down; 472}; 473 474int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 475void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 476ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 477 void *buffer, size_t size); 478ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 479 void *buffer, size_t size); 480 481/** 482 * drm_dp_dpcd_readb() - read a single byte from the DPCD 483 * @aux: DisplayPort AUX channel 484 * @offset: address of the register to read 485 * @valuep: location where the value of the register will be stored 486 * 487 * Returns the number of bytes transferred (1) on success, or a negative 488 * error code on failure. 489 */ 490static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 491 unsigned int offset, u8 *valuep) 492{ 493 return drm_dp_dpcd_read(aux, offset, valuep, 1); 494} 495 496/** 497 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 498 * @aux: DisplayPort AUX channel 499 * @offset: address of the register to write 500 * @value: value to write to the register 501 * 502 * Returns the number of bytes transferred (1) on success, or a negative 503 * error code on failure. 504 */ 505static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 506 unsigned int offset, u8 value) 507{ 508 return drm_dp_dpcd_write(aux, offset, &value, 1); 509} 510 511int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 512 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 513 514int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 515 u8 status[DP_LINK_STATUS_SIZE]); 516 517int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 518 enum drm_dp_phy dp_phy, 519 u8 link_status[DP_LINK_STATUS_SIZE]); 520 521bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 522 u8 real_edid_checksum); 523 524int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 525 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 526 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 527bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 528 const u8 port_cap[4], u8 type); 529bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 530 const u8 port_cap[4], 531 const struct drm_edid *drm_edid); 532int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 533 const u8 port_cap[4]); 534int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 535 const u8 port_cap[4], 536 const struct drm_edid *drm_edid); 537int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 538 const u8 port_cap[4], 539 const struct drm_edid *drm_edid); 540int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 541 const u8 port_cap[4], 542 const struct drm_edid *drm_edid); 543bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 544 const u8 port_cap[4]); 545bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 546 const u8 port_cap[4]); 547struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 548 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 549 const u8 port_cap[4]); 550int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 551void drm_dp_downstream_debug(struct seq_file *m, 552 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 553 const u8 port_cap[4], 554 const struct drm_edid *drm_edid, 555 struct drm_dp_aux *aux); 556enum drm_mode_subconnector 557drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 558 const u8 port_cap[4]); 559void drm_dp_set_subconnector_property(struct drm_connector *connector, 560 enum drm_connector_status status, 561 const u8 *dpcd, 562 const u8 port_cap[4]); 563 564struct drm_dp_desc; 565bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 566 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 567 const struct drm_dp_desc *desc); 568int drm_dp_read_sink_count(struct drm_dp_aux *aux); 569 570int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 571 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 572 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 573int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 574 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 575 enum drm_dp_phy dp_phy, 576 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 577int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 578int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 579int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 580bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 581bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 582 583void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 584void drm_dp_aux_init(struct drm_dp_aux *aux); 585int drm_dp_aux_register(struct drm_dp_aux *aux); 586void drm_dp_aux_unregister(struct drm_dp_aux *aux); 587 588int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 589int drm_dp_stop_crc(struct drm_dp_aux *aux); 590 591struct drm_dp_dpcd_ident { 592 u8 oui[3]; 593 u8 device_id[6]; 594 u8 hw_rev; 595 u8 sw_major_rev; 596 u8 sw_minor_rev; 597} __packed; 598 599/** 600 * struct drm_dp_desc - DP branch/sink device descriptor 601 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 602 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 603 */ 604struct drm_dp_desc { 605 struct drm_dp_dpcd_ident ident; 606 u32 quirks; 607}; 608 609int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 610 bool is_branch); 611 612/** 613 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 614 * 615 * Display Port sink and branch devices in the wild have a variety of bugs, try 616 * to collect them here. The quirks are shared, but it's up to the drivers to 617 * implement workarounds for them. 618 */ 619enum drm_dp_quirk { 620 /** 621 * @DP_DPCD_QUIRK_CONSTANT_N: 622 * 623 * The device requires main link attributes Mvid and Nvid to be limited 624 * to 16 bits. So will give a constant value (0x8000) for compatability. 625 */ 626 DP_DPCD_QUIRK_CONSTANT_N, 627 /** 628 * @DP_DPCD_QUIRK_NO_PSR: 629 * 630 * The device does not support PSR even if reports that it supports or 631 * driver still need to implement proper handling for such device. 632 */ 633 DP_DPCD_QUIRK_NO_PSR, 634 /** 635 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 636 * 637 * The device does not set SINK_COUNT to a non-zero value. 638 * The driver should ignore SINK_COUNT during detection. Note that 639 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 640 */ 641 DP_DPCD_QUIRK_NO_SINK_COUNT, 642 /** 643 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 644 * 645 * The device supports MST DSC despite not supporting Virtual DPCD. 646 * The DSC caps can be read from the physical aux instead. 647 */ 648 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 649 /** 650 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 651 * 652 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 653 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 654 */ 655 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 656 /** 657 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 658 * 659 * The device applies HBLANK expansion for some modes, but this 660 * requires enabling DSC. 661 */ 662 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 663}; 664 665/** 666 * drm_dp_has_quirk() - does the DP device have a specific quirk 667 * @desc: Device descriptor filled by drm_dp_read_desc() 668 * @quirk: Quirk to query for 669 * 670 * Return true if DP device identified by @desc has @quirk. 671 */ 672static inline bool 673drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 674{ 675 return desc->quirks & BIT(quirk); 676} 677 678/** 679 * struct drm_edp_backlight_info - Probed eDP backlight info struct 680 * @pwmgen_bit_count: The pwmgen bit count 681 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 682 * @max: The maximum backlight level that may be set 683 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 684 * @aux_enable: Does the panel support the AUX enable cap? 685 * @aux_set: Does the panel support setting the brightness through AUX? 686 * 687 * This structure contains various data about an eDP backlight, which can be populated by using 688 * drm_edp_backlight_init(). 689 */ 690struct drm_edp_backlight_info { 691 u8 pwmgen_bit_count; 692 u8 pwm_freq_pre_divider; 693 u16 max; 694 695 bool lsb_reg_used : 1; 696 bool aux_enable : 1; 697 bool aux_set : 1; 698}; 699 700int 701drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 702 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 703 u16 *current_level, u8 *current_mode); 704int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 705 u16 level); 706int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 707 u16 level); 708int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 709 710#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 711 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 712 713int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 714 715#else 716 717static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 718 struct drm_dp_aux *aux) 719{ 720 return 0; 721} 722 723#endif 724 725#ifdef CONFIG_DRM_DP_CEC 726void drm_dp_cec_irq(struct drm_dp_aux *aux); 727void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 728 struct drm_connector *connector); 729void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 730void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 731void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 732void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 733#else 734static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 735{ 736} 737 738static inline void 739drm_dp_cec_register_connector(struct drm_dp_aux *aux, 740 struct drm_connector *connector) 741{ 742} 743 744static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 745{ 746} 747 748static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 749 u16 source_physical_address) 750{ 751} 752 753static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 754 const struct edid *edid) 755{ 756} 757 758static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 759{ 760} 761 762#endif 763 764/** 765 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 766 * @link_rate: Requested Link rate from DPCD 0x219 767 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 768 * @phy_pattern: DP Phy test pattern from DPCD 0x248 769 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 770 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 771 * @enhanced_frame_cap: flag for enhanced frame capability. 772 */ 773struct drm_dp_phy_test_params { 774 int link_rate; 775 u8 num_lanes; 776 u8 phy_pattern; 777 u8 hbr2_reset[2]; 778 u8 custom80[10]; 779 bool enhanced_frame_cap; 780}; 781 782int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 783 struct drm_dp_phy_test_params *data); 784int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 785 struct drm_dp_phy_test_params *data, u8 dp_rev); 786int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 787 const u8 port_cap[4]); 788int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 789bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 790int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 791 u8 frl_mode); 792int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 793 u8 frl_type); 794int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 795int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 796 797bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 798int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 799void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 800 struct drm_connector *connector); 801bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 802int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 803int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 804int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 805int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 806int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 807int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 808bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 809 const u8 port_cap[4], u8 color_spc); 810int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 811 812#define DRM_DP_BW_OVERHEAD_MST BIT(0) 813#define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 814#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 815#define DRM_DP_BW_OVERHEAD_FEC BIT(3) 816#define DRM_DP_BW_OVERHEAD_DSC BIT(4) 817 818int drm_dp_bw_overhead(int lane_count, int hactive, 819 int dsc_slice_count, 820 int bpp_x16, unsigned long flags); 821int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 822int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 823 824ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 825 826#endif /* _DRM_DP_HELPER_H_ */ 827