Searched refs:devm_clk_hw_register_divider_parent_hw (Results 1 - 5 of 5) sorted by relevance
| /linux-master/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_10nm.c | 603 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
616 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
673 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, pclk_mux,
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| H A D | dsi_phy_7nm.c | 652 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
665 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
740 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
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| H A D | dsi_phy_28nm.c | 629 analog_postdiv = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
644 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
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| H A D | dsi_phy_28nm_8960.c | 438 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
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| /linux-master/include/linux/ |
| H A D | clk-provider.h | 895 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
906 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ macro
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