Searched refs:devm_clk_hw_register_divider (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/clk/
H A Dclk-loongson2.c252 hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node",
264 hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda",
270 hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu",
276 hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr",
282 hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac",
288 hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
H A Dclk-sp7021.c662 hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0,
/linux-master/drivers/clk/mediatek/
H A Dclk-mt8173-apmixedsys.c173 hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
/linux-master/drivers/iio/adc/
H A Daspeed_adc.c526 data->clk_prescaler = devm_clk_hw_register_divider(
542 data->clk_scaler = devm_clk_hw_register_divider(
/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1.c401 return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
409 return devm_clk_hw_register_divider(dev, name, parent,
/linux-master/include/linux/
H A Dclk-provider.h878 * devm_clk_hw_register_divider - register a divider clock with the clock framework
889 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ macro

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