Searched refs:devm_clk_hw_register_divider (Results 1 - 6 of 6) sorted by relevance
/linux-master/drivers/clk/ |
H A D | clk-loongson2.c | 252 hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node", 264 hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda", 270 hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu", 276 hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr", 282 hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac", 288 hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
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H A D | clk-sp7021.c | 662 hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0,
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-mt8173-apmixedsys.c | 173 hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
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/linux-master/drivers/iio/adc/ |
H A D | aspeed_adc.c | 526 data->clk_prescaler = devm_clk_hw_register_divider( 542 data->clk_scaler = devm_clk_hw_register_divider(
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/linux-master/drivers/clk/nuvoton/ |
H A D | clk-ma35d1.c | 401 return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, 409 return devm_clk_hw_register_divider(dev, name, parent,
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/linux-master/include/linux/ |
H A D | clk-provider.h | 878 * devm_clk_hw_register_divider - register a divider clock with the clock framework 889 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ macro
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