1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Aspeed AST2400/2500/2600 ADC 4 * 5 * Copyright (C) 2017 Google, Inc. 6 * Copyright (C) 2021 Aspeed Technology Inc. 7 * 8 * ADC clock formula: 9 * Ast2400/Ast2500: 10 * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1) 11 * Ast2600: 12 * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1) 13 */ 14 15#include <linux/clk.h> 16#include <linux/clk-provider.h> 17#include <linux/err.h> 18#include <linux/errno.h> 19#include <linux/io.h> 20#include <linux/module.h> 21#include <linux/of_platform.h> 22#include <linux/platform_device.h> 23#include <linux/regulator/consumer.h> 24#include <linux/reset.h> 25#include <linux/spinlock.h> 26#include <linux/types.h> 27#include <linux/bitfield.h> 28#include <linux/regmap.h> 29#include <linux/mfd/syscon.h> 30 31#include <linux/iio/iio.h> 32#include <linux/iio/driver.h> 33#include <linux/iopoll.h> 34 35#define ASPEED_RESOLUTION_BITS 10 36#define ASPEED_CLOCKS_PER_SAMPLE 12 37 38#define ASPEED_REG_ENGINE_CONTROL 0x00 39#define ASPEED_REG_INTERRUPT_CONTROL 0x04 40#define ASPEED_REG_VGA_DETECT_CONTROL 0x08 41#define ASPEED_REG_CLOCK_CONTROL 0x0C 42#define ASPEED_REG_COMPENSATION_TRIM 0xC4 43/* 44 * The register offset between 0xC8~0xCC can be read and won't affect the 45 * hardware logic in each version of ADC. 46 */ 47#define ASPEED_REG_MAX 0xD0 48 49#define ASPEED_ADC_ENGINE_ENABLE BIT(0) 50#define ASPEED_ADC_OP_MODE GENMASK(3, 1) 51#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 52#define ASPEED_ADC_OP_MODE_STANDBY 1 53#define ASPEED_ADC_OP_MODE_NORMAL 7 54#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) 55#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) 56/* 57 * Bit 6 determines not only the reference voltage range but also the dividing 58 * circuit for battery sensing. 59 */ 60#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) 61#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 62#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 63#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 64#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 65#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) 66#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 67#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 68#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) 69#define ASPEED_ADC_CH7_MODE BIT(12) 70#define ASPEED_ADC_CH7_NORMAL 0 71#define ASPEED_ADC_CH7_BAT 1 72#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) 73#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) 74#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) 75 76#define ASPEED_ADC_INIT_POLLING_TIME 500 77#define ASPEED_ADC_INIT_TIMEOUT 500000 78/* 79 * When the sampling rate is too high, the ADC may not have enough charging 80 * time, resulting in a low voltage value. Thus, the default uses a slow 81 * sampling rate for most use cases. 82 */ 83#define ASPEED_ADC_DEF_SAMPLING_RATE 65000 84 85struct aspeed_adc_trim_locate { 86 const unsigned int offset; 87 const unsigned int field; 88}; 89 90struct aspeed_adc_model_data { 91 const char *model_name; 92 unsigned int min_sampling_rate; // Hz 93 unsigned int max_sampling_rate; // Hz 94 unsigned int vref_fixed_mv; 95 bool wait_init_sequence; 96 bool need_prescaler; 97 bool bat_sense_sup; 98 u8 scaler_bit_width; 99 unsigned int num_channels; 100 const struct aspeed_adc_trim_locate *trim_locate; 101}; 102 103struct adc_gain { 104 u8 mult; 105 u8 div; 106}; 107 108struct aspeed_adc_data { 109 struct device *dev; 110 const struct aspeed_adc_model_data *model_data; 111 struct regulator *regulator; 112 void __iomem *base; 113 spinlock_t clk_lock; 114 struct clk_hw *fixed_div_clk; 115 struct clk_hw *clk_prescaler; 116 struct clk_hw *clk_scaler; 117 struct reset_control *rst; 118 int vref_mv; 119 u32 sample_period_ns; 120 int cv; 121 bool battery_sensing; 122 struct adc_gain battery_mode_gain; 123}; 124 125#define ASPEED_CHAN(_idx, _data_reg_addr) { \ 126 .type = IIO_VOLTAGE, \ 127 .indexed = 1, \ 128 .channel = (_idx), \ 129 .address = (_data_reg_addr), \ 130 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 131 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 132 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 133 BIT(IIO_CHAN_INFO_OFFSET), \ 134} 135 136static const struct iio_chan_spec aspeed_adc_iio_channels[] = { 137 ASPEED_CHAN(0, 0x10), 138 ASPEED_CHAN(1, 0x12), 139 ASPEED_CHAN(2, 0x14), 140 ASPEED_CHAN(3, 0x16), 141 ASPEED_CHAN(4, 0x18), 142 ASPEED_CHAN(5, 0x1A), 143 ASPEED_CHAN(6, 0x1C), 144 ASPEED_CHAN(7, 0x1E), 145 ASPEED_CHAN(8, 0x20), 146 ASPEED_CHAN(9, 0x22), 147 ASPEED_CHAN(10, 0x24), 148 ASPEED_CHAN(11, 0x26), 149 ASPEED_CHAN(12, 0x28), 150 ASPEED_CHAN(13, 0x2A), 151 ASPEED_CHAN(14, 0x2C), 152 ASPEED_CHAN(15, 0x2E), 153}; 154 155#define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \ 156 .type = IIO_VOLTAGE, \ 157 .indexed = 1, \ 158 .channel = (_idx), \ 159 .address = (_data_reg_addr), \ 160 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 161 BIT(IIO_CHAN_INFO_OFFSET), \ 162 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 163 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 164} 165static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = { 166 ASPEED_CHAN(0, 0x10), 167 ASPEED_CHAN(1, 0x12), 168 ASPEED_CHAN(2, 0x14), 169 ASPEED_CHAN(3, 0x16), 170 ASPEED_CHAN(4, 0x18), 171 ASPEED_CHAN(5, 0x1A), 172 ASPEED_CHAN(6, 0x1C), 173 ASPEED_BAT_CHAN(7, 0x1E), 174}; 175 176static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev) 177{ 178 struct device_node *syscon; 179 struct regmap *scu; 180 u32 scu_otp, trimming_val; 181 struct aspeed_adc_data *data = iio_priv(indio_dev); 182 183 syscon = of_find_node_by_name(NULL, "syscon"); 184 if (syscon == NULL) { 185 dev_warn(data->dev, "Couldn't find syscon node\n"); 186 return -EOPNOTSUPP; 187 } 188 scu = syscon_node_to_regmap(syscon); 189 of_node_put(syscon); 190 if (IS_ERR(scu)) { 191 dev_warn(data->dev, "Failed to get syscon regmap\n"); 192 return -EOPNOTSUPP; 193 } 194 if (data->model_data->trim_locate) { 195 if (regmap_read(scu, data->model_data->trim_locate->offset, 196 &scu_otp)) { 197 dev_warn(data->dev, 198 "Failed to get adc trimming data\n"); 199 trimming_val = 0x8; 200 } else { 201 trimming_val = 202 ((scu_otp) & 203 (data->model_data->trim_locate->field)) >> 204 __ffs(data->model_data->trim_locate->field); 205 if (!trimming_val) 206 trimming_val = 0x8; 207 } 208 dev_dbg(data->dev, 209 "trimming val = %d, offset = %08x, fields = %08x\n", 210 trimming_val, data->model_data->trim_locate->offset, 211 data->model_data->trim_locate->field); 212 writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM); 213 } 214 return 0; 215} 216 217static int aspeed_adc_compensation(struct iio_dev *indio_dev) 218{ 219 struct aspeed_adc_data *data = iio_priv(indio_dev); 220 u32 index, adc_raw = 0; 221 u32 adc_engine_control_reg_val; 222 223 adc_engine_control_reg_val = 224 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 225 adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; 226 adc_engine_control_reg_val |= 227 (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 228 ASPEED_ADC_ENGINE_ENABLE); 229 /* 230 * Enable compensating sensing: 231 * After that, the input voltage of ADC will force to half of the reference 232 * voltage. So the expected reading raw data will become half of the max 233 * value. We can get compensating value = 0x200 - ADC read raw value. 234 * It is recommended to average at least 10 samples to get a final CV. 235 */ 236 writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | 237 ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), 238 data->base + ASPEED_REG_ENGINE_CONTROL); 239 /* 240 * After enable compensating sensing mode need to wait some time for ADC stable 241 * Experiment result is 1ms. 242 */ 243 mdelay(1); 244 245 for (index = 0; index < 16; index++) { 246 /* 247 * Waiting for the sampling period ensures that the value acquired 248 * is fresh each time. 249 */ 250 ndelay(data->sample_period_ns); 251 adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); 252 } 253 adc_raw >>= 4; 254 data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; 255 writel(adc_engine_control_reg_val, 256 data->base + ASPEED_REG_ENGINE_CONTROL); 257 dev_dbg(data->dev, "Compensating value = %d\n", data->cv); 258 259 return 0; 260} 261 262static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) 263{ 264 struct aspeed_adc_data *data = iio_priv(indio_dev); 265 266 if (rate < data->model_data->min_sampling_rate || 267 rate > data->model_data->max_sampling_rate) 268 return -EINVAL; 269 /* Each sampling needs 12 clocks to convert.*/ 270 clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE); 271 rate = clk_get_rate(data->clk_scaler->clk); 272 data->sample_period_ns = DIV_ROUND_UP_ULL( 273 (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate); 274 dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate, 275 data->sample_period_ns); 276 277 return 0; 278} 279 280static int aspeed_adc_read_raw(struct iio_dev *indio_dev, 281 struct iio_chan_spec const *chan, 282 int *val, int *val2, long mask) 283{ 284 struct aspeed_adc_data *data = iio_priv(indio_dev); 285 u32 adc_engine_control_reg_val; 286 287 switch (mask) { 288 case IIO_CHAN_INFO_RAW: 289 if (data->battery_sensing && chan->channel == 7) { 290 adc_engine_control_reg_val = 291 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 292 writel(adc_engine_control_reg_val | 293 FIELD_PREP(ASPEED_ADC_CH7_MODE, 294 ASPEED_ADC_CH7_BAT) | 295 ASPEED_ADC_BAT_SENSING_ENABLE, 296 data->base + ASPEED_REG_ENGINE_CONTROL); 297 /* 298 * After enable battery sensing mode need to wait some time for adc stable 299 * Experiment result is 1ms. 300 */ 301 mdelay(1); 302 *val = readw(data->base + chan->address); 303 *val = (*val * data->battery_mode_gain.mult) / 304 data->battery_mode_gain.div; 305 /* Restore control register value */ 306 writel(adc_engine_control_reg_val, 307 data->base + ASPEED_REG_ENGINE_CONTROL); 308 } else 309 *val = readw(data->base + chan->address); 310 return IIO_VAL_INT; 311 312 case IIO_CHAN_INFO_OFFSET: 313 if (data->battery_sensing && chan->channel == 7) 314 *val = (data->cv * data->battery_mode_gain.mult) / 315 data->battery_mode_gain.div; 316 else 317 *val = data->cv; 318 return IIO_VAL_INT; 319 320 case IIO_CHAN_INFO_SCALE: 321 *val = data->vref_mv; 322 *val2 = ASPEED_RESOLUTION_BITS; 323 return IIO_VAL_FRACTIONAL_LOG2; 324 325 case IIO_CHAN_INFO_SAMP_FREQ: 326 *val = clk_get_rate(data->clk_scaler->clk) / 327 ASPEED_CLOCKS_PER_SAMPLE; 328 return IIO_VAL_INT; 329 330 default: 331 return -EINVAL; 332 } 333} 334 335static int aspeed_adc_write_raw(struct iio_dev *indio_dev, 336 struct iio_chan_spec const *chan, 337 int val, int val2, long mask) 338{ 339 switch (mask) { 340 case IIO_CHAN_INFO_SAMP_FREQ: 341 return aspeed_adc_set_sampling_rate(indio_dev, val); 342 343 case IIO_CHAN_INFO_SCALE: 344 case IIO_CHAN_INFO_RAW: 345 /* 346 * Technically, these could be written but the only reasons 347 * for doing so seem better handled in userspace. EPERM is 348 * returned to signal this is a policy choice rather than a 349 * hardware limitation. 350 */ 351 return -EPERM; 352 353 default: 354 return -EINVAL; 355 } 356} 357 358static int aspeed_adc_reg_access(struct iio_dev *indio_dev, 359 unsigned int reg, unsigned int writeval, 360 unsigned int *readval) 361{ 362 struct aspeed_adc_data *data = iio_priv(indio_dev); 363 364 if (!readval || reg % 4 || reg > ASPEED_REG_MAX) 365 return -EINVAL; 366 367 *readval = readl(data->base + reg); 368 369 return 0; 370} 371 372static const struct iio_info aspeed_adc_iio_info = { 373 .read_raw = aspeed_adc_read_raw, 374 .write_raw = aspeed_adc_write_raw, 375 .debugfs_reg_access = aspeed_adc_reg_access, 376}; 377 378static void aspeed_adc_unregister_fixed_divider(void *data) 379{ 380 struct clk_hw *clk = data; 381 382 clk_hw_unregister_fixed_factor(clk); 383} 384 385static void aspeed_adc_reset_assert(void *data) 386{ 387 struct reset_control *rst = data; 388 389 reset_control_assert(rst); 390} 391 392static void aspeed_adc_clk_disable_unprepare(void *data) 393{ 394 struct clk *clk = data; 395 396 clk_disable_unprepare(clk); 397} 398 399static void aspeed_adc_power_down(void *data) 400{ 401 struct aspeed_adc_data *priv_data = data; 402 403 writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), 404 priv_data->base + ASPEED_REG_ENGINE_CONTROL); 405} 406 407static void aspeed_adc_reg_disable(void *data) 408{ 409 struct regulator *reg = data; 410 411 regulator_disable(reg); 412} 413 414static int aspeed_adc_vref_config(struct iio_dev *indio_dev) 415{ 416 struct aspeed_adc_data *data = iio_priv(indio_dev); 417 int ret; 418 u32 adc_engine_control_reg_val; 419 420 if (data->model_data->vref_fixed_mv) { 421 data->vref_mv = data->model_data->vref_fixed_mv; 422 return 0; 423 } 424 adc_engine_control_reg_val = 425 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 426 data->regulator = devm_regulator_get_optional(data->dev, "vref"); 427 if (!IS_ERR(data->regulator)) { 428 ret = regulator_enable(data->regulator); 429 if (ret) 430 return ret; 431 ret = devm_add_action_or_reset( 432 data->dev, aspeed_adc_reg_disable, data->regulator); 433 if (ret) 434 return ret; 435 data->vref_mv = regulator_get_voltage(data->regulator); 436 /* Conversion from uV to mV */ 437 data->vref_mv /= 1000; 438 if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700)) 439 writel(adc_engine_control_reg_val | 440 FIELD_PREP( 441 ASPEED_ADC_REF_VOLTAGE, 442 ASPEED_ADC_REF_VOLTAGE_EXT_HIGH), 443 data->base + ASPEED_REG_ENGINE_CONTROL); 444 else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650)) 445 writel(adc_engine_control_reg_val | 446 FIELD_PREP( 447 ASPEED_ADC_REF_VOLTAGE, 448 ASPEED_ADC_REF_VOLTAGE_EXT_LOW), 449 data->base + ASPEED_REG_ENGINE_CONTROL); 450 else { 451 dev_err(data->dev, "Regulator voltage %d not support", 452 data->vref_mv); 453 return -EOPNOTSUPP; 454 } 455 } else { 456 if (PTR_ERR(data->regulator) != -ENODEV) 457 return PTR_ERR(data->regulator); 458 data->vref_mv = 2500000; 459 of_property_read_u32(data->dev->of_node, 460 "aspeed,int-vref-microvolt", 461 &data->vref_mv); 462 /* Conversion from uV to mV */ 463 data->vref_mv /= 1000; 464 if (data->vref_mv == 2500) 465 writel(adc_engine_control_reg_val | 466 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 467 ASPEED_ADC_REF_VOLTAGE_2500mV), 468 data->base + ASPEED_REG_ENGINE_CONTROL); 469 else if (data->vref_mv == 1200) 470 writel(adc_engine_control_reg_val | 471 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 472 ASPEED_ADC_REF_VOLTAGE_1200mV), 473 data->base + ASPEED_REG_ENGINE_CONTROL); 474 else { 475 dev_err(data->dev, "Voltage %d not support", data->vref_mv); 476 return -EOPNOTSUPP; 477 } 478 } 479 480 return 0; 481} 482 483static int aspeed_adc_probe(struct platform_device *pdev) 484{ 485 struct iio_dev *indio_dev; 486 struct aspeed_adc_data *data; 487 int ret; 488 u32 adc_engine_control_reg_val; 489 unsigned long scaler_flags = 0; 490 char clk_name[32], clk_parent_name[32]; 491 492 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data)); 493 if (!indio_dev) 494 return -ENOMEM; 495 496 data = iio_priv(indio_dev); 497 data->dev = &pdev->dev; 498 data->model_data = of_device_get_match_data(&pdev->dev); 499 platform_set_drvdata(pdev, indio_dev); 500 501 data->base = devm_platform_ioremap_resource(pdev, 0); 502 if (IS_ERR(data->base)) 503 return PTR_ERR(data->base); 504 505 /* Register ADC clock prescaler with source specified by device tree. */ 506 spin_lock_init(&data->clk_lock); 507 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s", 508 of_clk_get_parent_name(pdev->dev.of_node, 0)); 509 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div", 510 data->model_data->model_name); 511 data->fixed_div_clk = clk_hw_register_fixed_factor( 512 &pdev->dev, clk_name, clk_parent_name, 0, 1, 2); 513 if (IS_ERR(data->fixed_div_clk)) 514 return PTR_ERR(data->fixed_div_clk); 515 516 ret = devm_add_action_or_reset(data->dev, 517 aspeed_adc_unregister_fixed_divider, 518 data->fixed_div_clk); 519 if (ret) 520 return ret; 521 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name); 522 523 if (data->model_data->need_prescaler) { 524 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler", 525 data->model_data->model_name); 526 data->clk_prescaler = devm_clk_hw_register_divider( 527 &pdev->dev, clk_name, clk_parent_name, 0, 528 data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0, 529 &data->clk_lock); 530 if (IS_ERR(data->clk_prescaler)) 531 return PTR_ERR(data->clk_prescaler); 532 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), 533 clk_name); 534 scaler_flags = CLK_SET_RATE_PARENT; 535 } 536 /* 537 * Register ADC clock scaler downstream from the prescaler. Allow rate 538 * setting to adjust the prescaler as well. 539 */ 540 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler", 541 data->model_data->model_name); 542 data->clk_scaler = devm_clk_hw_register_divider( 543 &pdev->dev, clk_name, clk_parent_name, scaler_flags, 544 data->base + ASPEED_REG_CLOCK_CONTROL, 0, 545 data->model_data->scaler_bit_width, 546 data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0, 547 &data->clk_lock); 548 if (IS_ERR(data->clk_scaler)) 549 return PTR_ERR(data->clk_scaler); 550 551 data->rst = devm_reset_control_get_shared(&pdev->dev, NULL); 552 if (IS_ERR(data->rst)) { 553 dev_err(&pdev->dev, 554 "invalid or missing reset controller device tree entry"); 555 return PTR_ERR(data->rst); 556 } 557 reset_control_deassert(data->rst); 558 559 ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert, 560 data->rst); 561 if (ret) 562 return ret; 563 564 ret = aspeed_adc_vref_config(indio_dev); 565 if (ret) 566 return ret; 567 568 ret = aspeed_adc_set_trim_data(indio_dev); 569 if (ret) 570 return ret; 571 572 if (of_find_property(data->dev->of_node, "aspeed,battery-sensing", 573 NULL)) { 574 if (data->model_data->bat_sense_sup) { 575 data->battery_sensing = 1; 576 if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) & 577 ASPEED_ADC_BAT_SENSING_DIV) { 578 data->battery_mode_gain.mult = 3; 579 data->battery_mode_gain.div = 1; 580 } else { 581 data->battery_mode_gain.mult = 3; 582 data->battery_mode_gain.div = 2; 583 } 584 } else 585 dev_warn(&pdev->dev, 586 "Failed to enable battery-sensing mode\n"); 587 } 588 589 ret = clk_prepare_enable(data->clk_scaler->clk); 590 if (ret) 591 return ret; 592 ret = devm_add_action_or_reset(data->dev, 593 aspeed_adc_clk_disable_unprepare, 594 data->clk_scaler->clk); 595 if (ret) 596 return ret; 597 ret = aspeed_adc_set_sampling_rate(indio_dev, 598 ASPEED_ADC_DEF_SAMPLING_RATE); 599 if (ret) 600 return ret; 601 602 adc_engine_control_reg_val = 603 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 604 adc_engine_control_reg_val |= 605 FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 606 ASPEED_ADC_ENGINE_ENABLE; 607 /* Enable engine in normal mode. */ 608 writel(adc_engine_control_reg_val, 609 data->base + ASPEED_REG_ENGINE_CONTROL); 610 611 ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down, 612 data); 613 if (ret) 614 return ret; 615 616 if (data->model_data->wait_init_sequence) { 617 /* Wait for initial sequence complete. */ 618 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, 619 adc_engine_control_reg_val, 620 adc_engine_control_reg_val & 621 ASPEED_ADC_CTRL_INIT_RDY, 622 ASPEED_ADC_INIT_POLLING_TIME, 623 ASPEED_ADC_INIT_TIMEOUT); 624 if (ret) 625 return ret; 626 } 627 628 aspeed_adc_compensation(indio_dev); 629 /* Start all channels in normal mode. */ 630 adc_engine_control_reg_val = 631 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 632 adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL; 633 writel(adc_engine_control_reg_val, 634 data->base + ASPEED_REG_ENGINE_CONTROL); 635 636 indio_dev->name = data->model_data->model_name; 637 indio_dev->info = &aspeed_adc_iio_info; 638 indio_dev->modes = INDIO_DIRECT_MODE; 639 indio_dev->channels = data->battery_sensing ? 640 aspeed_adc_iio_bat_channels : 641 aspeed_adc_iio_channels; 642 indio_dev->num_channels = data->model_data->num_channels; 643 644 ret = devm_iio_device_register(data->dev, indio_dev); 645 return ret; 646} 647 648static const struct aspeed_adc_trim_locate ast2500_adc_trim = { 649 .offset = 0x154, 650 .field = GENMASK(31, 28), 651}; 652 653static const struct aspeed_adc_trim_locate ast2600_adc0_trim = { 654 .offset = 0x5d0, 655 .field = GENMASK(3, 0), 656}; 657 658static const struct aspeed_adc_trim_locate ast2600_adc1_trim = { 659 .offset = 0x5d0, 660 .field = GENMASK(7, 4), 661}; 662 663static const struct aspeed_adc_model_data ast2400_model_data = { 664 .model_name = "ast2400-adc", 665 .vref_fixed_mv = 2500, 666 .min_sampling_rate = 10000, 667 .max_sampling_rate = 500000, 668 .need_prescaler = true, 669 .scaler_bit_width = 10, 670 .num_channels = 16, 671}; 672 673static const struct aspeed_adc_model_data ast2500_model_data = { 674 .model_name = "ast2500-adc", 675 .vref_fixed_mv = 1800, 676 .min_sampling_rate = 1, 677 .max_sampling_rate = 1000000, 678 .wait_init_sequence = true, 679 .need_prescaler = true, 680 .scaler_bit_width = 10, 681 .num_channels = 16, 682 .trim_locate = &ast2500_adc_trim, 683}; 684 685static const struct aspeed_adc_model_data ast2600_adc0_model_data = { 686 .model_name = "ast2600-adc0", 687 .min_sampling_rate = 10000, 688 .max_sampling_rate = 500000, 689 .wait_init_sequence = true, 690 .bat_sense_sup = true, 691 .scaler_bit_width = 16, 692 .num_channels = 8, 693 .trim_locate = &ast2600_adc0_trim, 694}; 695 696static const struct aspeed_adc_model_data ast2600_adc1_model_data = { 697 .model_name = "ast2600-adc1", 698 .min_sampling_rate = 10000, 699 .max_sampling_rate = 500000, 700 .wait_init_sequence = true, 701 .bat_sense_sup = true, 702 .scaler_bit_width = 16, 703 .num_channels = 8, 704 .trim_locate = &ast2600_adc1_trim, 705}; 706 707static const struct of_device_id aspeed_adc_matches[] = { 708 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, 709 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, 710 { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data }, 711 { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data }, 712 {}, 713}; 714MODULE_DEVICE_TABLE(of, aspeed_adc_matches); 715 716static struct platform_driver aspeed_adc_driver = { 717 .probe = aspeed_adc_probe, 718 .driver = { 719 .name = KBUILD_MODNAME, 720 .of_match_table = aspeed_adc_matches, 721 } 722}; 723 724module_platform_driver(aspeed_adc_driver); 725 726MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); 727MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver"); 728MODULE_LICENSE("GPL"); 729