Searched refs:csr_base_addr (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
38 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
42 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
45 #define READ_CSR_STAT(csr_base_addr, bank) \
46 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \
49 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \
52 ADF_CSR_RD((csr_base_addr)
101 read_base(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
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H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) argument
35 return READ_CSR_STAT(csr_base_addr, ban
38 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank) argument
43 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) argument
48 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank) argument
53 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank) argument
58 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank) argument
63 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank) argument
68 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank) argument
73 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank) argument
78 write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
84 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
90 write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring, u32 value) argument
96 read_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
102 write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring, dma_addr_t addr) argument
108 read_csr_int_en(void __iomem *csr_base_addr, u32 bank) argument
113 write_csr_int_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
118 read_csr_int_flag(void __iomem *csr_base_addr, u32 bank) argument
123 write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value) argument
129 read_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank) argument
134 write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank) argument
139 write_csr_int_srcsel_w_val(void __iomem *csr_base_addr, u32 bank, u32 value) argument
145 read_csr_int_col_en(void __iomem *csr_base_addr, u32 bank) argument
150 write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
155 read_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank) argument
160 write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank, u32 value) argument
166 read_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank) argument
171 write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank, u32 value) argument
177 read_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank) argument
182 write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
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H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) argument
35 return READ_CSR_E_STAT(csr_base_addr, ban
38 write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring, u32 value) argument
44 write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring, dma_addr_t addr) argument
50 write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value) argument
55 write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank) argument
60 write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
66 write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank, u32 value) argument
72 write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank, u32 value) argument
78 write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank, u32 value) argument
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H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZ
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H A Dadf_accel_devices.h180 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
182 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
184 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
186 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
188 u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
189 u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
190 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
191 u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
192 u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
193 u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u3
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