1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2024 Intel Corporation */ 3#ifndef ADF_GEN4_HW_CSR_DATA_H_ 4#define ADF_GEN4_HW_CSR_DATA_H_ 5 6#include <linux/bitops.h> 7#include "adf_accel_devices.h" 8 9#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 10#define ADF_RING_CSR_RING_CONFIG 0x1000 11#define ADF_RING_CSR_RING_LBASE 0x1040 12#define ADF_RING_CSR_RING_UBASE 0x1080 13#define ADF_RING_CSR_RING_HEAD 0x0C0 14#define ADF_RING_CSR_RING_TAIL 0x100 15#define ADF_RING_CSR_STAT 0x140 16#define ADF_RING_CSR_UO_STAT 0x148 17#define ADF_RING_CSR_E_STAT 0x14C 18#define ADF_RING_CSR_NE_STAT 0x150 19#define ADF_RING_CSR_NF_STAT 0x154 20#define ADF_RING_CSR_F_STAT 0x158 21#define ADF_RING_CSR_C_STAT 0x15C 22#define ADF_RING_CSR_INT_FLAG_EN 0x16C 23#define ADF_RING_CSR_INT_FLAG 0x170 24#define ADF_RING_CSR_INT_SRCSEL 0x174 25#define ADF_RING_CSR_INT_COL_EN 0x17C 26#define ADF_RING_CSR_INT_COL_CTL 0x180 27#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 28#define ADF_RING_CSR_EXP_STAT 0x188 29#define ADF_RING_CSR_EXP_INT_EN 0x18C 30#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 31#define ADF_RING_CSR_ADDR_OFFSET 0x100000 32#define ADF_RING_BUNDLE_SIZE 0x2000 33#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 34 35#define BUILD_RING_BASE_ADDR(addr, size) \ 36 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 37#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 38 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 39 ADF_RING_BUNDLE_SIZE * (bank) + \ 40 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 41#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 42 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 43 ADF_RING_BUNDLE_SIZE * (bank) + \ 44 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 45#define READ_CSR_STAT(csr_base_addr, bank) \ 46 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT) 48#define READ_CSR_UO_STAT(csr_base_addr, bank) \ 49 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT) 51#define READ_CSR_E_STAT(csr_base_addr, bank) \ 52 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT) 54#define READ_CSR_NE_STAT(csr_base_addr, bank) \ 55 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 56 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NE_STAT) 57#define READ_CSR_NF_STAT(csr_base_addr, bank) \ 58 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 59 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NF_STAT) 60#define READ_CSR_F_STAT(csr_base_addr, bank) \ 61 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 62 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_F_STAT) 63#define READ_CSR_C_STAT(csr_base_addr, bank) \ 64 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 65 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_C_STAT) 66#define READ_CSR_EXP_STAT(csr_base_addr, bank) \ 67 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 68 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_STAT) 69#define READ_CSR_EXP_INT_EN(csr_base_addr, bank) \ 70 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 71 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_INT_EN) 72#define WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value) \ 73 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 74 ADF_RING_BUNDLE_SIZE * (bank) + \ 75 ADF_RING_CSR_EXP_INT_EN, value) 76#define READ_CSR_RING_CONFIG(csr_base_addr, bank, ring) \ 77 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 78 ADF_RING_BUNDLE_SIZE * (bank) + \ 79 ADF_RING_CSR_RING_CONFIG + ((ring) << 2)) 80#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 81 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 82 ADF_RING_BUNDLE_SIZE * (bank) + \ 83 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value) 84#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 85do { \ 86 void __iomem *_csr_base_addr = csr_base_addr; \ 87 u32 _bank = bank; \ 88 u32 _ring = ring; \ 89 dma_addr_t _value = value; \ 90 u32 l_base = 0, u_base = 0; \ 91 l_base = lower_32_bits(_value); \ 92 u_base = upper_32_bits(_value); \ 93 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 94 ADF_RING_BUNDLE_SIZE * (_bank) + \ 95 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \ 96 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 97 ADF_RING_BUNDLE_SIZE * (_bank) + \ 98 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \ 99} while (0) 100 101static inline u64 read_base(void __iomem *csr_base_addr, u32 bank, u32 ring) 102{ 103 u32 l_base, u_base; 104 105 /* 106 * Use special IO wrapper for ring base as LBASE and UBASE are 107 * not physically contigious 108 */ 109 l_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + 110 ADF_RING_CSR_RING_LBASE + (ring << 2)); 111 u_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + 112 ADF_RING_CSR_RING_UBASE + (ring << 2)); 113 114 return (u64)u_base << 32 | (u64)l_base; 115} 116 117#define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ 118 read_base((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, (bank), (ring)) 119 120#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 121 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 122 ADF_RING_BUNDLE_SIZE * (bank) + \ 123 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value) 124#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 125 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 126 ADF_RING_BUNDLE_SIZE * (bank) + \ 127 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value) 128#define READ_CSR_INT_EN(csr_base_addr, bank) \ 129 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 130 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG_EN) 131#define WRITE_CSR_INT_EN(csr_base_addr, bank, value) \ 132 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 133 ADF_RING_BUNDLE_SIZE * (bank) + \ 134 ADF_RING_CSR_INT_FLAG_EN, (value)) 135#define READ_CSR_INT_FLAG(csr_base_addr, bank) \ 136 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 137 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG) 138#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 139 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 140 ADF_RING_BUNDLE_SIZE * (bank) + \ 141 ADF_RING_CSR_INT_FLAG, (value)) 142#define READ_CSR_INT_SRCSEL(csr_base_addr, bank) \ 143 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 144 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_SRCSEL) 145#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 146 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 147 ADF_RING_BUNDLE_SIZE * (bank) + \ 148 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK) 149#define WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value) \ 150 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 151 ADF_RING_BUNDLE_SIZE * (bank) + \ 152 ADF_RING_CSR_INT_SRCSEL, (value)) 153#define READ_CSR_INT_COL_EN(csr_base_addr, bank) \ 154 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 155 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_EN) 156#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 157 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 158 ADF_RING_BUNDLE_SIZE * (bank) + \ 159 ADF_RING_CSR_INT_COL_EN, (value)) 160#define READ_CSR_INT_COL_CTL(csr_base_addr, bank) \ 161 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 162 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_CTL) 163#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 164 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 165 ADF_RING_BUNDLE_SIZE * (bank) + \ 166 ADF_RING_CSR_INT_COL_CTL, \ 167 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 168#define READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank) \ 169 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 170 ADF_RING_BUNDLE_SIZE * (bank) + \ 171 ADF_RING_CSR_INT_FLAG_AND_COL) 172#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 173 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 174 ADF_RING_BUNDLE_SIZE * (bank) + \ 175 ADF_RING_CSR_INT_FLAG_AND_COL, (value)) 176 177#define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \ 178 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 179 ADF_RING_BUNDLE_SIZE * (bank) + \ 180 ADF_RING_CSR_RING_SRV_ARB_EN) 181#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 182 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 183 ADF_RING_BUNDLE_SIZE * (bank) + \ 184 ADF_RING_CSR_RING_SRV_ARB_EN, (value)) 185 186void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops); 187 188#endif 189