1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright(c) 2024 Intel Corporation */ 3#include <linux/types.h> 4#include "adf_gen2_hw_csr_data.h" 5 6static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size) 7{ 8 return BUILD_RING_BASE_ADDR(addr, size); 9} 10 11static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) 12{ 13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); 14} 15 16static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, 17 u32 value) 18{ 19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); 20} 21 22static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) 23{ 24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); 25} 26 27static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, 28 u32 value) 29{ 30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); 31} 32 33static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) 34{ 35 return READ_CSR_E_STAT(csr_base_addr, bank); 36} 37 38static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, 39 u32 ring, u32 value) 40{ 41 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value); 42} 43 44static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring, 45 dma_addr_t addr) 46{ 47 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); 48} 49 50static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value) 51{ 52 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); 53} 54 55static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank) 56{ 57 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); 58} 59 60static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, 61 u32 value) 62{ 63 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); 64} 65 66static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank, 67 u32 value) 68{ 69 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); 70} 71 72static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank, 73 u32 value) 74{ 75 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value); 76} 77 78static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank, 79 u32 value) 80{ 81 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value); 82} 83 84void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops) 85{ 86 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; 87 csr_ops->read_csr_ring_head = read_csr_ring_head; 88 csr_ops->write_csr_ring_head = write_csr_ring_head; 89 csr_ops->read_csr_ring_tail = read_csr_ring_tail; 90 csr_ops->write_csr_ring_tail = write_csr_ring_tail; 91 csr_ops->read_csr_e_stat = read_csr_e_stat; 92 csr_ops->write_csr_ring_config = write_csr_ring_config; 93 csr_ops->write_csr_ring_base = write_csr_ring_base; 94 csr_ops->write_csr_int_flag = write_csr_int_flag; 95 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel; 96 csr_ops->write_csr_int_col_en = write_csr_int_col_en; 97 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl; 98 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col; 99 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en; 100} 101EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops); 102