| /linux-master/drivers/cpufreq/ |
| H A D | tegra124-cpufreq.c | 20 struct clk *cpu_clk; member in struct:tegra124_cpufreq_priv
32 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
36 orig_parent = clk_get_parent(priv->cpu_clk);
37 clk_set_parent(priv->cpu_clk, priv->pllp_clk);
43 clk_set_parent(priv->cpu_clk, priv->dfll_clk);
48 clk_set_parent(priv->cpu_clk, orig_parent);
73 priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
74 if (IS_ERR(priv->cpu_clk)) {
75 ret = PTR_ERR(priv->cpu_clk);
124 clk_put(priv->cpu_clk);
[all...] |
| H A D | highbank-cpufreq.c | 62 struct clk *cpu_clk; local
82 cpu_clk = clk_get(cpu_dev, NULL);
83 if (IS_ERR(cpu_clk)) {
84 ret = PTR_ERR(cpu_clk);
89 ret = clk_notifier_register(cpu_clk, &hb_cpufreq_clk_nb);
|
| H A D | kirkwood-cpufreq.c | 21 struct clk *cpu_clk; member in struct:priv
65 clk_set_parent(priv.powersave_clk, priv.cpu_clk);
119 priv.cpu_clk = of_clk_get_by_name(np, "cpu_clk");
120 if (IS_ERR(priv.cpu_clk)) {
122 err = PTR_ERR(priv.cpu_clk);
126 err = clk_prepare_enable(priv.cpu_clk);
132 kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000;
174 clk_disable_unprepare(priv.cpu_clk);
187 clk_disable_unprepare(priv.cpu_clk);
[all...] |
| H A D | mediatek-cpufreq.c | 45 struct clk *cpu_clk; member in struct:mtk_cpu_dvfs_info
204 struct clk *cpu_clk = policy->clk; local
205 struct clk *armpll = clk_get_parent(cpu_clk);
214 pre_freq_hz = clk_get_rate(cpu_clk);
265 ret = clk_set_parent(cpu_clk, info->inter_clk);
278 clk_set_parent(cpu_clk, armpll);
284 ret = clk_set_parent(cpu_clk, armpll);
301 clk_set_parent(cpu_clk, info->inter_clk);
303 clk_set_parent(cpu_clk, armpll);
409 info->cpu_clk
[all...] |
| H A D | cpufreq-dt.c | 107 struct clk *cpu_clk; local
118 cpu_clk = clk_get(cpu_dev, NULL);
119 if (IS_ERR(cpu_clk)) {
120 ret = PTR_ERR(cpu_clk);
131 policy->clk = cpu_clk;
149 clk_put(cpu_clk);
|
| H A D | qcom-cpufreq-hw.c | 58 struct clk_hw cpu_clk; member in struct:qcom_cpufreq_data
624 struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk);
705 data->cpu_clk.init = &clk_init;
707 ret = devm_clk_hw_register(dev, &data->cpu_clk);
714 clk_data->hws[i] = &data->cpu_clk;
|
| /linux-master/arch/arm/mach-mvebu/ |
| H A D | platsmp.c | 39 struct clk *cpu_clk; local
44 cpu_clk = of_clk_get(np, 0);
45 if (WARN_ON(IS_ERR(cpu_clk)))
47 return cpu_clk;
101 struct clk *cpu_clk = get_cpu_clk(cpu); local
103 if (!cpu_clk || !boot_cpu_clk)
106 clk_prepare_enable(cpu_clk);
107 clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));
|
| /linux-master/arch/sh/kernel/cpu/ |
| H A D | clock-cpg.c | 24 static struct clk cpu_clk = { variable in typeref:struct:clk
36 &cpu_clk,
44 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
|
| /linux-master/arch/mips/lantiq/xway/ |
| H A D | clk.c | 144 unsigned int ocp_sel, cpu_clk; local
147 cpu_clk = ltq_vr9_cpu_hz();
153 clk = cpu_clk;
157 clk = cpu_clk / 2;
161 clk = (cpu_clk * 2) / 5;
165 clk = cpu_clk / 3;
|
| /linux-master/drivers/clk/mvebu/ |
| H A D | clk-cpu.c | 33 struct cpu_clk { struct
46 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
113 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
168 struct cpu_clk *cpuclk;
|
| /linux-master/drivers/clk/sunxi-ng/ |
| H A D | ccu-suniv-f1c100s.c | 110 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
327 &cpu_clk.common,
419 [CLK_CPU] = &cpu_clk.common.hw,
529 .common = &cpu_clk.common,
530 .cm = &cpu_clk.mux,
|
| H A D | ccu-sun8i-v3s.c | 142 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
400 &cpu_clk.common,
501 [CLK_CPU] = &cpu_clk.common.hw,
581 [CLK_CPU] = &cpu_clk.common.hw,
|
| H A D | ccu-sun5i.c | 180 static struct ccu_mux cpu_clk = { variable in typeref:struct:ccu_mux
520 &cpu_clk.common,
648 [CLK_CPU] = &cpu_clk.common.hw,
787 [CLK_CPU] = &cpu_clk.common.hw,
893 [CLK_CPU] = &cpu_clk.common.hw,
|
| H A D | ccu-sun8i-r40.c | 264 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
816 &cpu_clk.common,
1019 [CLK_CPU] = &cpu_clk.common.hw,
1273 .common = &cpu_clk.common,
1274 .cm = &cpu_clk.mux,
|
| H A D | ccu-sun6i-a31.c | 182 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
818 &cpu_clk.common,
1006 [CLK_CPU] = &cpu_clk.common.hw,
1224 .common = &cpu_clk.common,
1225 .cm = &cpu_clk.mux,
|
| H A D | ccu-sun4i-a10.c | 223 static struct ccu_mux cpu_clk = { variable in typeref:struct:ccu_mux
876 &cpu_clk.common,
1079 [CLK_CPU] = &cpu_clk.common.hw,
1232 [CLK_CPU] = &cpu_clk.common.hw,
|
| /linux-master/drivers/clk/ralink/ |
| H A D | clk-mt7621.c | 263 unsigned long cpu_clk; local
274 cpu_clk = 500000000;
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
283 cpu_clk = xtal_clk;
286 return cpu_clk / ffiv * ffrac;
|
| /linux-master/drivers/base/ |
| H A D | arch_topology.c | 312 struct clk *cpu_clk; local
342 cpu_clk = of_clk_get(cpu_node, 0);
343 if (!PTR_ERR_OR_ZERO(cpu_clk)) {
345 clk_get_rate(cpu_clk) / HZ_PER_KHZ;
346 clk_put(cpu_clk);
|
| /linux-master/arch/arc/kernel/ |
| H A D | setup.c | 576 struct clk *cpu_clk; local
590 cpu_clk = clk_get(cpu_dev, NULL);
591 if (IS_ERR(cpu_clk)) {
595 freq = clk_get_rate(cpu_clk);
|
| /linux-master/drivers/pmdomain/qcom/ |
| H A D | cpr.c | 235 struct clk *cpu_clk; member in struct:cpr_drv
1305 if (!drv->cpu_clk) {
1311 rate = clk_get_rate(drv->cpu_clk);
1471 drv->cpu_clk = devm_clk_get(dev, NULL);
1472 if (IS_ERR(drv->cpu_clk)) {
1473 ret = PTR_ERR(drv->cpu_clk);
|
| /linux-master/drivers/clk/actions/ |
| H A D | owl-s900.c | 114 static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
511 &cpu_clk.common,
604 [CLK_CPU] = &cpu_clk.common.hw,
|
| /linux-master/kernel/sched/ |
| H A D | debug.c | 832 u64 ktime, sched_clk, cpu_clk; local
838 cpu_clk = local_clock();
852 PN(cpu_clk);
|
| /linux-master/drivers/clk/meson/ |
| H A D | meson8b.c | 782 .name = "cpu_clk",
3744 struct clk_hw *cpu_clk; member in struct:meson8b_nb_data
3758 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
3763 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
3770 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
3850 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK];
|
| H A D | g12a.c | 507 .name = "cpu_clk",
527 .name = "cpu_clk",
957 * to feed cpu_clk, this is the current path :
958 * cpu_clk
982 * Now, cpu_clk is 24MHz in the current path :
983 * cpu_clk
1007 * cpu_clk
1046 struct clk_hw *cpu_clk; member in struct:g12a_sys_pll_nb_data
1060 * to feed cpu_clk, this the current path :
1061 * cpu_clk
[all...] |