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c8c525b0 |
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18-Nov-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi-ng: Allow drivers to be built as modules While it is useful to build all of the CCU drivers at once, only 1-3 of them will be loaded at a time, or possibly none of them if the kernel is booted on a non-sunxi platform. These CCU drivers are relatively large; 32-bit drivers have 30-50k of data each, while the 64-bit ones are 50-75k due to the increased pointer overhead. About half of that data comes from relocations. Let's allow the user to build these drivers as modules so only the necessary data is loaded. As a first step, convert the CCUs that are already platform drivers. When the drivers are built as modules, normally the file name becomes the module name. However, the current file names are inconsistent with the <platform>-<peripheral> name used everywhere else: the devicetree bindings, the platform driver names, and the Kconfig symbols. Use Makfile logic to rename the modules so they follow the usual pattern. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-3-samuel@sholland.org
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605c99ff |
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07-Sep-2021 |
Cai Huoqing <caihuoqing@baidu.com> |
clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085228.4764-1-caihuoqing@baidu.com
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66028ddb |
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31-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi-ng: Prevent unbinding CCUs via sysfs The CCU drivers are not really designed to be unbound. Unbinding a SoC's main CCU is especially pointless, as very few of the peripherals on the SoC will work without it. Let's avoid any potential problems by removing the bind/unbind attributes from sysfs for these drivers. This change is not applied to the "secondary" CCUs (DE, USB) as those could reasonably be unbound without making the system useless. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210901050526.45673-3-samuel@sholland.org
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9bec2b9c |
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31-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi-ng: Unregister clocks/resets when unbinding Currently, unbinding a CCU driver unmaps the device's MMIO region, while leaving its clocks/resets and their providers registered. This can cause a page fault later when some clock operation tries to perform MMIO. Fix this by separating the CCU initialization from the memory allocation, and then using a devres callback to unregister the clocks and resets. This also fixes a memory leak of the `struct ccu_reset`, and uses the correct owner (the specific platform driver) for the clocks and resets. Early OF clock providers are never unregistered, and limited error handling is possible, so they are mostly unchanged. The error reporting is made more consistent by moving the message inside of_sunxi_ccu_probe. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210901050526.45673-2-samuel@sholland.org
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a3ba99a2 |
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25-Aug-2020 |
Jernej Skrabec <jernej.skrabec@siol.net> |
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL Audio cores need specific clock rates which can't be simply obtained by adjusting integer multipliers and dividers. HW for such cases supports delta-sigma modulation which enables fractional multipliers. Port H3 delta-sigma table to R40. They have identical audio PLLs. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825131049.1277596-1-jernej.skrabec@siol.net
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c7b30526 |
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17-Dec-2019 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs One of the uses of the external clock outputs is to provide a stable 32768 Hz clock signal to WiFi and Bluetooth chips. On the R40, the RTC has an internal RC oscillator that is muxed with the external crystal. Allow setting the parent rate for the external clock outputs so that requests for 32768 Hz get passed to the RTC's clock driver to mux in the external crystal if it isn't already muxed correctly. Fixes: cd030a78f7aa ("clk: sunxi-ng: support R40 SoC") Fixes: 01a7ea763fc4 ("clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output") Cc: <stable@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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3fccf2ed |
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03-May-2019 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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9c92ab61 |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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62e59c4e |
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18-Apr-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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01a7ea76 |
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28-Nov-2018 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output On the R40, in addition to a mux between the RTC's own RC oscillator and an external 32768 Hz crystal, which are muxed inside the RTC module, the CCU also has its own RC oscillator, which runs at around 2 MHz, and can be muxed with the LOSC output from the RTC. This muxed output is called "SYS 32K" in the module clock diagram, but otherwise referred to as the LOSC throughout the CCU documentation. The RC oscillator is not very accurate, even though it has an undocumented calibration function. We really want a precise clock at 32768 Hz, instead of something at around 32 KHz. This patch forces the SYS 32K clock to use the RTC output as its parent, and doesn't bother registering the internal oscillator nor a clock mux. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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b16fb669 |
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09-Aug-2018 |
Jernej Skrabec <jernej.skrabec@siol.net> |
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs Video PLLs on R40 can be set to higher rate that it is actually supported by HW. Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP clock driver. Interestengly, user manual specifies maximum frequency to be 600 MHz. Historically, this data was wrong in some user manuals for other SoCs, so more faith is put in BSP clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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fb4aa0f6 |
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25-Jun-2018 |
Jernej Skrabec <jernej.skrabec@siol.net> |
clk: sunxi-ng: r40: Allow setting parent rate to display related clocks Display related peripherals need precise clocks to operate correctly. Allow DE2, TCONs and HDMI to set parent clock. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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24a95f75 |
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25-Jun-2018 |
Jernej Skrabec <jernej.skrabec@siol.net> |
clk: sunxi-ng: r40: Add minimal rate for video PLLs According to documentation and experience with other similar SoCs, video PLLs don't work stable if their output frequency is set below 192 MHz. Because of that, set minimal rate to both R40 video PLLs to 192 MHz. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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17de4c85 |
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01-May-2018 |
Icenowy Zheng <icenowy@aosc.io> |
clk: sunxi-ng: r40: export a regmap to access the GMAC register There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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c3bf29f6 |
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01-May-2018 |
Icenowy Zheng <icenowy@aosc.io> |
clk: sunxi-ng: r40: rewrite init code to a platform driver As we need to register a regmap on the R40 CCU, there needs to be a device structure bound to the CCU device node. Rewrite the R40 CCU driver initial code to make it a proper platform driver, thus we will have a platform device bound to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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cd030a78 |
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14-Aug-2017 |
Icenowy Zheng <icenowy@aosc.io> |
clk: sunxi-ng: support R40 SoC Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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