/linux-master/drivers/gpu/drm/amd/display/dc/bios/ |
H A D | command_table.h | 76 enum controller_id controller_id, 80 enum controller_id controller_id, 90 enum controller_id crtc_id,
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H A D | command_table_helper2.h | 41 enum controller_id id,
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H A D | command_table2.h | 76 enum controller_id controller_id, 80 enum controller_id controller_id, 90 enum controller_id crtc_id,
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H A D | command_table_helper.h | 41 enum controller_id id,
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H A D | command_table_helper_struct.h | 35 bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
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H A D | command_table.c | 1019 if (CONTROLLER_ID_D1 != bp_params->controller_id) 1052 uint8_t controller_id; local 1059 bp_params->controller_id, &controller_id)) { 1060 clk.sPCLKInput.ucCRTC = controller_id; 1122 uint8_t controller_id; local 1129 bp_params->controller_id, &controller_id)) { 1149 clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id; 1214 uint8_t controller_id; local 2004 enable_crtc_v1( struct bios_parser *bp, enum controller_id controller_id, bool enable) argument 2054 enable_crtc_mem_req_v1( struct bios_parser *bp, enum controller_id controller_id, bool enable) argument [all...] |
H A D | command_table2.c | 441 uint8_t controller_id; local 448 controller_id, &controller_id)) { 468 clk.crtc_id = controller_id; 488 bp_params->target_pixel_clock_100hz, (int)controller_id, 571 bp_params->controller_id, &atom_controller_id)) 663 enum controller_id controller_id, 682 enum controller_id controller_id, 680 enable_crtc_v1( struct bios_parser *bp, enum controller_id controller_id, bool enable) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce100/ |
H A D | dce100_hwseq.h | 45 bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
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H A D | dce100_hwseq.c | 74 uint8_t controller_id, 89 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){ 92 dcb, controller_id + 1, cntl); 98 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id), 72 dce100_enable_display_power_gating( struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce120/ |
H A D | dce120_hwseq.c | 78 #define CNTL_ID(controller_id)\ 79 controller_id 83 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) 90 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id * 96 value, 0, DCP, controller_id, 101 value, 1, DCP, controller_id, 106 value, 1, DCP, controller_id, 152 uint8_t controller_id, 169 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { 172 dcb, controller_id 150 dce120_enable_display_power_gating( struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | abm.h | 42 bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst); 50 unsigned int controller_id,
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce112/ |
H A D | dce112_hwseq.c | 115 uint8_t controller_id, 130 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { 133 dcb, controller_id + 1, cntl); 139 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 113 dce112_enable_display_power_gating( struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_abm.c | 58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) argument 75 MASTER_COMM_CMD_REG_BYTE1, controller_id); 90 uint32_t controller_id, 103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); 113 if (controller_id == 0) 234 unsigned int controller_id, 245 controller_id, 86 dmcu_set_backlight_level( struct dce_abm *abm_dce, uint32_t backlight_pwm_u16_16, uint32_t frame_ramp, uint32_t controller_id, uint32_t panel_id) argument 230 dce_abm_set_backlight_level_pwm( struct abm *abm, unsigned int backlight_pwm_u16_16, unsigned int frame_ramp, unsigned int controller_id, unsigned int panel_inst) argument
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/linux-master/drivers/scsi/aic94xx/ |
H A D | aic94xx_sds.h | 66 struct controller_id { struct 85 struct controller_id contrl_id; /*PCI id to identify the controller */
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/linux-master/drivers/gpu/drm/amd/display/include/ |
H A D | bios_parser_types.h | 137 enum controller_id controller_id; member in struct:bp_crtc_source_select 170 enum controller_id controller_id; member in struct:bp_hw_crtc_timing_parameters 218 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member in struct:bp_pixel_clock_parameters
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H A D | grph_object_id.h | 74 enum controller_id { enum 255 static inline enum controller_id dal_graphics_object_id_get_controller_id( 259 return (enum controller_id) id.id;
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/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_8_0_sc8280xp.h | 320 .controller_id = MSM_DP_CONTROLLER_0, 329 .controller_id = MSM_DSI_CONTROLLER_0, 339 .controller_id = MSM_DSI_CONTROLLER_1, 349 .controller_id = MSM_DP_CONTROLLER_0, 358 .controller_id = MSM_DP_CONTROLLER_1, 367 .controller_id = MSM_DP_CONTROLLER_3, 376 .controller_id = MSM_DP_CONTROLLER_2, 385 .controller_id = MSM_DP_CONTROLLER_2, 394 .controller_id = MSM_DP_CONTROLLER_1,
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H A D | dpu_9_2_x1e80100.h | 334 .controller_id = MSM_DP_CONTROLLER_0, 343 .controller_id = MSM_DSI_CONTROLLER_0, 353 .controller_id = MSM_DSI_CONTROLLER_1, 363 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 372 .controller_id = MSM_DP_CONTROLLER_1, 381 .controller_id = MSM_DP_CONTROLLER_3, 390 .controller_id = MSM_DP_CONTROLLER_2, 399 .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ 408 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
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H A D | dpu_5_1_sc8180x.h | 306 .controller_id = MSM_DP_CONTROLLER_0, 315 .controller_id = MSM_DSI_CONTROLLER_0, 325 .controller_id = MSM_DSI_CONTROLLER_1, 337 .controller_id = 999, 346 .controller_id = MSM_DP_CONTROLLER_1, 355 .controller_id = MSM_DP_CONTROLLER_2,
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H A D | dpu_7_2_sc7280.h | 188 .controller_id = MSM_DP_CONTROLLER_0, 197 .controller_id = MSM_DSI_CONTROLLER_0, 207 .controller_id = MSM_DP_CONTROLLER_1,
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H A D | dpu_3_0_msm8998.h | 242 .controller_id = MSM_DP_CONTROLLER_0, 250 .controller_id = MSM_DSI_CONTROLLER_0, 258 .controller_id = MSM_DSI_CONTROLLER_1,
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H A D | dpu_3_2_sdm660.h | 201 .controller_id = MSM_DP_CONTROLLER_0, 210 .controller_id = MSM_DSI_CONTROLLER_0, 219 .controller_id = MSM_DSI_CONTROLLER_1,
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/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_bios_types.h | 102 enum controller_id id, 125 enum controller_id controller_id,
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | clock_source.h | 92 enum controller_id controller_id; member in struct:pixel_clk_params
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/linux-master/drivers/gpu/drm/amd/display/dc/dce110/ |
H A D | dce110_timing_generator.h | 101 enum controller_id controller_id; member in struct:dce110_timing_generator
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