Searched refs:clock_cfg (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.c226 u64 clock_cfg; local
275 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
276 clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
292 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
293 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
314 u64 clock_cfg; local
321 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
322 clock_cfg
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.h51 struct dc_clock_config *clock_cfg);
H A Ddcn20_clk_mgr.c452 struct dc_clock_config *clock_cfg)
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
457 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
458 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
463 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
464 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
449 dcn2_get_clock(struct clk_mgr *clk_mgr, struct dc_state *context, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) argument
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c372 u64 clock_cfg; local
398 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
403 clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK;
404 clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN;
408 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE;
410 clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK;
411 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN;
414 clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
415 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
416 clock_cfg
469 u64 clock_cfg; local
575 u64 clock_cfg; local
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/linux-master/drivers/clk/stm32/
H A Dclk-stm32-core.h50 void *clock_cfg; member in struct:clock_config
167 .clock_cfg = (_struct) {_clk},\
H A Dclk-stm32-core.c633 struct clk_stm32_mux *mux = cfg->clock_cfg;
654 struct clk_stm32_gate *gate = cfg->clock_cfg;
675 struct clk_stm32_div *div = cfg->clock_cfg;
696 struct clk_stm32_composite *composite = cfg->clock_cfg;
/linux-master/drivers/spi/
H A Dspi-fsi.c369 u64 clock_cfg = 0ULL; local
409 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
413 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.h188 struct dc_clock_config *clock_cfg);
H A Ddcn10_hwseq.c3902 struct dc_clock_config clock_cfg = {0}; local
3909 context, clock_type, &clock_cfg);
3911 if (clk_khz > clock_cfg.max_clock_khz)
3914 if (clk_khz < clock_cfg.min_clock_khz)
3917 if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
3937 struct dc_clock_config *clock_cfg)
3942 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3935 dcn10_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) argument
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h296 struct dc_clock_config *clock_cfg);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h327 struct dc_clock_config *clock_cfg);
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2336 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c4814 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) argument
4817 dc->hwss.get_clock(dc, clock_type, clock_cfg);

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