Searched refs:clk_type (Results 1 - 25 of 52) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
91 (clk_type)
254 enum dm_pp_clock_type clk_type; member in struct:dm_pp_clock_for_voltage_req
[all...]
H A Ddm_services.h184 * input: clk_type - display clk / sclk / mem clk
192 enum dm_pp_clock_type clk_type,
197 enum dm_pp_clock_type clk_type,
202 enum dm_pp_clock_type clk_type,
/linux-master/drivers/clk/imx/
H A Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type)
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
58 int num_parents, u32 rsrc_id, u8 clk_type)
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
51 imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type) argument
57 imx_clk_scu2(const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) argument
H A Dclk-scu.c33 u8 clk_type; member in struct:imx_scu_clk_node
47 * @clk_type: type of this clock resource
52 u8 clk_type; member in struct:clk_scu
243 msg.data.req.clk = clk->clk_type;
334 msg.clk = clk->clk_type;
352 msg.data.req.clk = clk->clk_type;
379 msg.clk = clk->clk_type;
424 clk->clk_type, true, false);
439 clk->clk_type, false, false);
471 u32 rsrc_id, u8 clk_type)
469 __imx_clk_scu(struct device *dev, const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) argument
687 imx_clk_scu_alloc_dev(const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) argument
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c597 enum smu_clk_type clk_type,
603 if (!clk_table || clk_type >= SMU_CLK_COUNT)
606 switch (clk_type) {
651 enum smu_clk_type clk_type,
657 if (!clk_table || clk_type >= SMU_CLK_COUNT)
660 switch (clk_type) {
695 enum smu_clk_type clk_type,
700 smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
702 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
708 enum smu_clk_type clk_type)
596 smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
650 smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
694 smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
707 smu_v14_0_0_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) argument
738 smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
858 smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
970 smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
983 smu_v14_0_0_get_current_clk_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
1016 smu_v14_0_1_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
1047 smu_v14_0_0_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
1076 smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
1088 smu_v14_0_0_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
1163 smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1210 smu_v14_0_0_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
[all...]
H A Dsmu_v14_0.c935 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, argument
942 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
943 switch (clk_type) {
971 clk_type);
1004 enum smu_clk_type clk_type,
1011 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1016 clk_type);
1041 enum smu_clk_type clk_type,
1051 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1056 clk_type);
1003 smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1040 smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1266 smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint16_t level, uint32_t *value) argument
1300 smu_v14_0_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
1311 smu_v14_0_get_fine_grained_status(struct smu_context *smu, enum smu_clk_type clk_type, bool *is_fine_grained_dpm) argument
1349 smu_v14_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, struct smu_14_0_dpm_table *single_dpm_table) argument
[all...]
/linux-master/sound/soc/intel/skylake/
H A Dskl-ssp-clk.c57 static int skl_get_vbus_id(u32 index, u8 clk_type) argument
59 switch (clk_type) {
74 static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type) argument
84 if (clk_type == SKL_SCLK_FS) {
107 u32 vbus_id, u8 clk_type,
125 if (clk_type == SKL_SCLK_FS) {
132 if (clk_type == SKL_SCLK)
181 int vbus_id, clk_type; local
183 clk_type = skl_get_clk_type(clkdev->id);
184 if (clk_type <
105 skl_send_clk_dma_control(struct skl_dev *skl, struct skl_clk_rate_cfg_table *rcfg, u32 vbus_id, u8 clk_type, bool enable) argument
219 int clk_type; local
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_4_ppt.c387 enum smu_clk_type clk_type,
392 switch (clk_type) {
423 enum smu_clk_type clk_type,
429 if (!clk_table || clk_type >= SMU_CLK_COUNT)
432 switch (clk_type) {
467 enum smu_clk_type clk_type,
472 switch (clk_type) {
496 enum smu_clk_type clk_type, char *buf)
504 switch (clk_type) {
523 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type,
386 smu_v13_0_4_get_current_clk_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
422 smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
466 smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
495 smu_v13_0_4_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
713 smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) argument
742 smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
851 smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
900 smu_v13_0_4_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
934 smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu, enum amd_dpm_forced_level level, enum smu_clk_type clk_type, uint32_t *min_clk, uint32_t *max_clk) argument
[all...]
H A Dsmu_v13_0_5_ppt.c587 enum smu_clk_type clk_type,
592 switch (clk_type) {
618 enum smu_clk_type clk_type,
623 switch (clk_type) {
647 enum smu_clk_type clk_type,
653 if (!clk_table || clk_type >= SMU_CLK_COUNT)
656 switch (clk_type) {
691 enum smu_clk_type clk_type)
695 switch (clk_type) {
720 enum smu_clk_type clk_type,
586 smu_v13_0_5_get_current_clk_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
617 smu_v13_0_5_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
646 smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
690 smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) argument
719 smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
829 smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
874 smu_v13_0_5_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
948 smu_v13_0_5_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
982 smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu, enum amd_dpm_forced_level level, enum smu_clk_type clk_type, uint32_t *min_clk, uint32_t *max_clk) argument
[all...]
H A Dyellow_carp_ppt.c718 enum smu_clk_type clk_type,
723 switch (clk_type) {
752 enum smu_clk_type clk_type,
757 switch (clk_type) {
781 enum smu_clk_type clk_type,
787 if (!clk_table || clk_type >= SMU_CLK_COUNT)
790 switch (clk_type) {
825 enum smu_clk_type clk_type)
829 switch (clk_type) {
854 enum smu_clk_type clk_type,
717 yellow_carp_get_current_clk_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
751 yellow_carp_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *count) argument
780 yellow_carp_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t dpm_level, uint32_t *freq) argument
824 yellow_carp_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) argument
853 yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
963 yellow_carp_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1018 yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu, enum smu_clk_type clk_type) argument
1054 yellow_carp_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
1130 yellow_carp_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
1166 yellow_carp_get_dpm_profile_freq(struct smu_context *smu, enum amd_dpm_forced_level level, enum smu_clk_type clk_type, uint32_t *min_clk, uint32_t *max_clk) argument
[all...]
H A Dsmu_v13_0.c1084 enum amd_pp_clock_type clk_type = clock_req->clock_type; local
1091 switch (clk_type) {
1554 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, argument
1561 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1562 switch (clk_type) {
1590 clk_type);
1623 enum smu_clk_type clk_type,
1630 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1635 clk_type);
1660 enum smu_clk_type clk_type,
1622 smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1659 smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1897 smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint16_t level, uint32_t *value) argument
1930 smu_v13_0_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
1944 smu_v13_0_get_fine_grained_status(struct smu_context *smu, enum smu_clk_type clk_type, bool *is_fine_grained_dpm) argument
1982 smu_v13_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, struct smu_13_0_dpm_table *single_dpm_table) argument
[all...]
/linux-master/drivers/nfc/s3fwrn5/
H A Dnci.h44 __u8 clk_type; member in struct:nci_prop_fw_cfg_cmd
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v11_0.h254 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
257 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
261 enum smu_clk_type clk_type,
272 enum smu_clk_type clk_type,
277 enum smu_clk_type clk_type,
281 enum smu_clk_type clk_type,
285 enum smu_clk_type clk_type,
H A Dsmu_v12_0.h58 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
H A Dsmu_v14_0.h172 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
175 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
179 enum smu_clk_type clk_type,
190 enum smu_clk_type clk_type,
H A Dsmu_v13_0.h218 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
221 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
225 enum smu_clk_type clk_type,
236 enum smu_clk_type clk_type,
240 enum smu_clk_type clk_type, uint16_t level,
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, argument
207 if (!clk_table || clk_type >= SMU_CLK_COUNT)
210 switch (clk_type) {
281 enum smu_clk_type clk_type,
289 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
290 switch (clk_type) {
325 switch (clk_type) {
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
353 switch (clk_type) {
280 renoir_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
494 renoir_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
697 enum smu_clk_type clk_type; local
724 enum smu_clk_type clk_type; local
727 enum smu_clk_type clk_type; member in struct:clk_feature_map
797 renoir_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
[all...]
H A Dsmu_v12_0.c213 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, argument
218 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
221 switch (clk_type) {
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type,
120 switch (clk_type) {
294 enum dm_pp_clock_type clk_type,
303 dc_to_pp_clock_type(clk_type), &pp_clks)) {
305 get_default_clock_levels(clk_type, dc_clks);
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
345 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
361 enum dm_pp_clock_type clk_type,
369 dc_to_pp_clock_type(clk_type),
110 get_default_clock_levels( enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels *clks) argument
292 dm_pp_get_clock_levels_by_type( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels *dc_clks) argument
359 dm_pp_get_clock_levels_by_type_with_latency( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_latency *clk_level_info) argument
379 dm_pp_get_clock_levels_by_type_with_voltage( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_voltage *clk_level_info) argument
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c515 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, argument
520 if (!clk_table || clk_type >= SMU_CLK_COUNT)
523 switch (clk_type) {
559 enum smu_clk_type clk_type, char *buf)
576 switch (clk_type) {
631 switch (clk_type) {
638 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
639 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
661 enum smu_clk_type clk_type, cha
558 vangogh_print_legacy_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
660 vangogh_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
788 vangogh_common_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
855 vangogh_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) argument
887 vangogh_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
1081 vangogh_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1163 vangogh_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
1274 enum smu_clk_type clk_type; local
1302 enum smu_clk_type clk_type; local
1305 enum smu_clk_type clk_type; member in struct:clk_feature_map
[all...]
H A Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type,
265 switch (clk_type) {
291 enum smu_clk_type clk_type,
300 switch (clk_type) {
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
536 enum smu_clk_type clk_type,
543 switch (clk_type) {
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low);
259 cyan_skillfish_get_current_clk_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
290 cyan_skillfish_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
535 cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
H A Dsmu_v11_0.c1057 enum amd_pp_clock_type clk_type = clock_req->clock_type; local
1064 switch (clk_type) {
1704 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, argument
1711 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1712 switch (clk_type) {
1740 clk_type);
1764 enum smu_clk_type clk_type,
1771 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1776 clk_type);
1801 enum smu_clk_type clk_type,
1763 smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1800 smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
1957 smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint16_t level, uint32_t *value) argument
1995 smu_v11_0_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) argument
2005 smu_v11_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, struct smu_11_0_dpm_table *single_dpm_table) argument
2043 smu_v11_0_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min_value, uint32_t *max_value) argument
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c62 enum smu_clk_type clk_type,
132 enum smu_clk_type clk_type,
140 clk_type,
148 enum smu_clk_type clk_type,
159 clk_type,
464 enum smu_clk_type clk_type; local
466 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
471 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type))
131 smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) argument
147 smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) argument
2378 smu_force_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) argument
2409 enum smu_clk_type clk_type; local
2776 smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) argument
2791 enum smu_clk_type clk_type; local
2848 enum smu_clk_type clk_type; local
2860 enum smu_clk_type clk_type; local
3146 enum smu_clk_type clk_type; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);

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