Searched refs:clk_hw_register_gate (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835-aux.c43 clk_hw_register_gate(dev, "aux_uart", parent, 0, gate, 0, 0, NULL);
46 clk_hw_register_gate(dev, "aux_spi1", parent, 0, gate, 1, 0, NULL);
49 clk_hw_register_gate(dev, "aux_spi2", parent, 0, gate, 2, 0, NULL);
H A Dclk-bcm63xx-gate.c519 clk = clk_hw_register_gate(&pdev->dev, entry->name, NULL,
H A Dclk-bcm2835.c1502 return clk_hw_register_gate(cprman->dev, gate_data->name,
/linux-master/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c136 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
142 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
145 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
148 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
151 clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
154 clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
157 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
H A Dclk-exynos-audss.c211 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
215 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
219 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
223 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
230 clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
235 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
H A Dclk.c248 clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
/linux-master/drivers/clk/x86/
H A Dclk-fch.c73 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
83 hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
/linux-master/drivers/clk/
H A Dclk-gate_test.c19 ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL,
38 ret = clk_hw_register_gate(NULL, "test_gate", "test_parent", 0, NULL,
109 ret = clk_hw_register_gate(NULL, "test_gate", NULL, 0, NULL,
391 hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7,
406 hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7,
421 hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 2,
436 hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 29,
H A Dclk-ast2600.c80 * This borrows from clk_hw_register_gate, but registers two 'gates', one
549 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
566 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
594 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
602 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
624 hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
632 hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
H A Dclk-asm9260.c295 clk_hw_register_gate(NULL, gd->name,
314 hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,
H A Dclk-aspeed.c444 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
474 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
482 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
H A Dclk-gate.c192 hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
H A Dclk-gemini.c342 clk_hw_register_gate(NULL, gd->name,
H A Dclk-stm32f4.c1731 clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
1821 clks[idx] = clk_hw_register_gate(
H A Dclk-bm1880.c730 hw = clk_hw_register_gate(NULL, clks[i].name,
H A Dclk-stm32h7.c1334 hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c118 return clk_hw_register_gate(dev, clk_name, parent_name,
/linux-master/arch/arm/mach-ep93xx/
H A Dclock.c523 hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id,
617 hw = clk_hw_register_gate(NULL, "ohci-platform",
/linux-master/drivers/clk/berlin/
H A Dbg2q.c354 hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
H A Dbg2.c660 hws[CLKID_GETH0 + n] = clk_hw_register_gate(NULL, gd->name,
/linux-master/drivers/clk/imx/
H A Dclk-imx7ulp.c204 hws[IMX7ULP_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
H A Dclk.h379 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
/linux-master/include/linux/
H A Dclk-provider.h546 * clk_hw_register_gate - register a gate clock with the clock framework
556 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ macro
/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp1.c399 return clk_hw_register_gate(dev,

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