Searched refs:clk_hw_register_divider (Results 1 - 18 of 18) sorted by relevance
/linux-master/drivers/clk/samsung/ |
H A D | clk-exynos-audss.c | 199 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", 203 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, 207 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
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H A D | clk-s5pv210-audss.c | 129 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, 132 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
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H A D | clk.c | 225 clk_hw = clk_hw_register_divider(ctx->dev, list->name,
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/linux-master/drivers/clk/ |
H A D | clk-loongson2.c | 306 hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0", 312 hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
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H A D | clk-asm9260.c | 304 hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
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H A D | clk-nomadik.c | 538 hw = clk_hw_register_divider(NULL, clk_name, parent_name,
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H A D | clk-npcm7xx.c | 488 hw = clk_hw_register_divider(NULL, div_data->name,
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H A D | clk-stm32h7.c | 1250 hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0, 1254 hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
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H A D | clk-stm32f4.c | 1848 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
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/linux-master/drivers/clk/imx/ |
H A D | clk.h | 361 return clk_hw_register_divider(NULL, name, parent, 0, 370 return clk_hw_register_divider(NULL, name, parent, flags,
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H A D | clk-imx6sll.c | 177 hws[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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H A D | clk-imx6sl.c | 268 hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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H A D | clk-imx6ul.c | 234 hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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H A D | clk-imx6sx.c | 250 hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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H A D | clk-imx6q.c | 602 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-mtk.c | 417 hw = clk_hw_register_divider(dev, mcd->name, mcd->parent_name,
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/linux-master/include/linux/ |
H A D | clk-provider.h | 760 * clk_hw_register_divider - register a divider clock with the clock framework 771 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ macro
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/linux-master/drivers/clk/renesas/ |
H A D | rzg2l-cpg.c | 431 clk_hw = clk_hw_register_divider(dev, core->name,
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