Searched refs:clk_hw_register_divider (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/clk/samsung/
H A Dclk-exynos-audss.c199 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
203 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
207 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
H A Dclk-s5pv210-audss.c129 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
132 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
H A Dclk.c225 clk_hw = clk_hw_register_divider(ctx->dev, list->name,
/linux-master/drivers/clk/
H A Dclk-loongson2.c306 hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
312 hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
H A Dclk-asm9260.c304 hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
H A Dclk-nomadik.c538 hw = clk_hw_register_divider(NULL, clk_name, parent_name,
H A Dclk-npcm7xx.c488 hw = clk_hw_register_divider(NULL, div_data->name,
H A Dclk-stm32h7.c1250 hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
1254 hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
H A Dclk-stm32f4.c1848 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
/linux-master/drivers/clk/imx/
H A Dclk.h361 return clk_hw_register_divider(NULL, name, parent, 0,
370 return clk_hw_register_divider(NULL, name, parent, flags,
H A Dclk-imx6sll.c177 hws[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
H A Dclk-imx6sl.c268 hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
H A Dclk-imx6ul.c234 hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
H A Dclk-imx6sx.c250 hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
H A Dclk-imx6q.c602 hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
/linux-master/drivers/clk/mediatek/
H A Dclk-mtk.c417 hw = clk_hw_register_divider(dev, mcd->name, mcd->parent_name,
/linux-master/include/linux/
H A Dclk-provider.h760 * clk_hw_register_divider - register a divider clock with the clock framework
771 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ macro
/linux-master/drivers/clk/renesas/
H A Drzg2l-cpg.c431 clk_hw = clk_hw_register_divider(dev, core->name,

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