Searched refs:cgs_write_register (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu7_smumgr.c43 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
108 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
144 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
181 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
182 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
201 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
285 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
460 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
464 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
504 cgs_write_register(hwmg
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H A Dsmu8_smumgr.c88 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
90 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
91 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
125 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
141 cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
157 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
195 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
204 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
208 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
212 cgs_write_register(hwmg
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H A Diceland_smumgr.c166 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
171 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
2617 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2618 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2619 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2620 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2621 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2622 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2623 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2624 cgs_write_register(hwmg
[all...]
H A Dci_smumgr.c103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
213 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
214 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
230 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
2334 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
2339 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
2690 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2691 cgs_write_register(hwmg
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H A Dtonga_smumgr.c3081 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
3083 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
3085 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
3087 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
3089 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
3091 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
3093 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
3095 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
3097 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
3099 cgs_write_register(hwmg
[all...]
H A Dfiji_smumgr.c213 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
215 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
217 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
2523 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
2525 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
2527 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
2529 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
2531 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
2533 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
2535 cgs_write_register(hwmg
[all...]
H A Dpolaris10_smumgr.c111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
/linux-master/drivers/gpu/drm/amd/include/
H A Dcgs_common.h93 * cgs_write_register() - Write an MMIO register
131 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
166 #define cgs_write_register(dev, offset, value) \ macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_acp.c456 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
474 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
492 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
525 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
542 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h163 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
H A Dsmu_helper.c151 cgs_write_register(hwmgr->device, indirect_port, index);
188 cgs_write_register(hwmgr->device, indirect_port, index);
H A Dvega10_powertune.c793 cgs_write_register(hwmgr->device, config_regs->offset, data);
986 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
1100 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
H A Dsmu7_powertune.c946 cgs_write_register(hwmgr->device, config_regs->offset, data);
981 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
1010 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
H A Dsmu7_hwmgr.c205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
538 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
539 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
543 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
544 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
553 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1285 cgs_write_register(hwmgr->device, 0x1488,
4764 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c11433 cgs_write_register(ctx->cgs_device, address, value);

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