Searched refs:cfg5 (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/gpu/drm/v3d/
H A Dv3d_trace.h187 TP_PROTO(struct drm_device *dev, u32 cfg5, u32 cfg6),
188 TP_ARGS(dev, cfg5, cfg6),
192 __field(u32, cfg5)
198 __entry->cfg5 = cfg5;
204 __entry->cfg5,
/linux-master/arch/mips/kvm/
H A Dmips.c1375 unsigned int sr, cfg5; local
1397 cfg5 = kvm_read_c0_guest_config5(cop0);
1398 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1419 unsigned int sr, cfg5; local
1441 cfg5 = kvm_read_c0_guest_config5(cop0);
1442 change_c0_config5(MIPS_CONF5_FRE, cfg5);
/linux-master/drivers/hwmon/
H A Dlm85.c59 ((data)->type == adt7468 && !((data)->cfg5 & ADT7468_OFF64))
61 ((data)->type == adt7468 && !((data)->cfg5 & ADT7468_HFPWM))
316 u8 cfg5; /* Config Register 5 on ADT7468 */ member in struct:lm85_data
417 data->cfg5 = lm85_read_value(client, ADT7468_REG_CFG5);
814 data->cfg5 &= ~ADT7468_HFPWM;
815 lm85_write_value(client, ADT7468_REG_CFG5, data->cfg5);
823 data->cfg5 |= ADT7468_HFPWM;
824 lm85_write_value(client, ADT7468_REG_CFG5, data->cfg5);
/linux-master/drivers/memory/tegra/
H A Dtegra210-emc-core.c1224 u32 cmd_pad, dq_pad, rfu1, cfg5, common_tx, ramp_up_wait = 0; local
1235 cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX];
1313 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
1319 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
1325 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
1339 u32 ramp_down_wait = 0, cmd_pad, dq_pad, rfu1, cfg5, common_tx; local
1351 cfg5 = entry->burst_regs[EMC_FBIO_CFG5_INDEX];
1357 ccfifo_writel(emc, cfg5 | EMC_FBIO_CFG5_CMD_TX_DIS,
/linux-master/drivers/net/ethernet/realtek/
H A D8139too.c2314 u8 cfg5 = RTL_R8 (Config5); local
2326 if (cfg5 & Cfg5_UWF)
2328 if (cfg5 & Cfg5_MWF)
2330 if (cfg5 & Cfg5_BWF)
2345 u8 cfg3, cfg5; local
2364 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2369 cfg5 |= Cfg5_UWF;
2371 cfg5 |= Cfg5_MWF;
2373 cfg5 |= Cfg5_BWF;
2374 RTL_W8 (Config5, cfg5); /* nee
[all...]
/linux-master/drivers/net/ethernet/broadcom/
H A Dtg3.c15245 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0; local
15266 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15421 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)

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