1/* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringstr��m - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90*/ 91 92#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94#define DRV_NAME "8139too" 95#define DRV_VERSION "0.9.28" 96 97 98#include <linux/module.h> 99#include <linux/kernel.h> 100#include <linux/compiler.h> 101#include <linux/pci.h> 102#include <linux/init.h> 103#include <linux/interrupt.h> 104#include <linux/netdevice.h> 105#include <linux/etherdevice.h> 106#include <linux/rtnetlink.h> 107#include <linux/delay.h> 108#include <linux/ethtool.h> 109#include <linux/mii.h> 110#include <linux/completion.h> 111#include <linux/crc32.h> 112#include <linux/io.h> 113#include <linux/uaccess.h> 114#include <linux/gfp.h> 115#include <linux/if_vlan.h> 116#include <asm/irq.h> 117 118#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 119 120/* Default Message level */ 121#define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 122 NETIF_MSG_PROBE | \ 123 NETIF_MSG_LINK) 124 125 126/* define to 1, 2 or 3 to enable copious debugging info */ 127#define RTL8139_DEBUG 0 128 129/* define to 1 to disable lightweight runtime debugging checks */ 130#undef RTL8139_NDEBUG 131 132 133#ifdef RTL8139_NDEBUG 134# define assert(expr) do {} while (0) 135#else 136# define assert(expr) \ 137 if (unlikely(!(expr))) { \ 138 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 139 #expr, __FILE__, __func__, __LINE__); \ 140 } 141#endif 142 143 144/* A few user-configurable values. */ 145/* media options */ 146#define MAX_UNITS 8 147static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 148static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 149 150/* Whether to use MMIO or PIO. Default to MMIO. */ 151#ifdef CONFIG_8139TOO_PIO 152static bool use_io = true; 153#else 154static bool use_io = false; 155#endif 156 157/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 158 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 159static int multicast_filter_limit = 32; 160 161/* bitmapped message enable number */ 162static int debug = -1; 163 164/* 165 * Receive ring size 166 * Warning: 64K ring has hardware issues and may lock up. 167 */ 168#if defined(CONFIG_SH_DREAMCAST) 169#define RX_BUF_IDX 0 /* 8K ring */ 170#else 171#define RX_BUF_IDX 2 /* 32K ring */ 172#endif 173#define RX_BUF_LEN (8192 << RX_BUF_IDX) 174#define RX_BUF_PAD 16 175#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 176 177#if RX_BUF_LEN == 65536 178#define RX_BUF_TOT_LEN RX_BUF_LEN 179#else 180#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 181#endif 182 183/* Number of Tx descriptor registers. */ 184#define NUM_TX_DESC 4 185 186/* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/ 187#define MAX_ETH_FRAME_SIZE 1792 188 189/* max supported payload size */ 190#define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 191 192/* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */ 193#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 194#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 195 196/* PCI Tuning Parameters 197 Threshold is bytes transferred to chip before transmission starts. */ 198#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 199 200/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 201#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 202#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 203#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 204#define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 205 206/* Operational parameters that usually are not changed. */ 207/* Time in jiffies before concluding the transmitter is hung. */ 208#define TX_TIMEOUT (6*HZ) 209 210 211enum { 212 HAS_MII_XCVR = 0x010000, 213 HAS_CHIP_XCVR = 0x020000, 214 HAS_LNK_CHNG = 0x040000, 215}; 216 217#define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 218#define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 219#define RTL_MIN_IO_SIZE 0x80 220#define RTL8139B_IO_SIZE 256 221 222#define RTL8129_CAPS HAS_MII_XCVR 223#define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 224 225typedef enum { 226 RTL8139 = 0, 227 RTL8129, 228} board_t; 229 230 231/* indexed by board_t, above */ 232static const struct { 233 const char *name; 234 u32 hw_flags; 235} board_info[] = { 236 { "RealTek RTL8139", RTL8139_CAPS }, 237 { "RealTek RTL8129", RTL8129_CAPS }, 238}; 239 240 241static const struct pci_device_id rtl8139_pci_tbl[] = { 242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 261 {0x16ec, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 262 263#ifdef CONFIG_SH_SECUREEDGE5410 264 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 266#endif 267#ifdef CONFIG_8139TOO_8129 268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 269#endif 270 271 /* some crazy cards report invalid vendor ids like 272 * 0x0001 here. The other ids are valid and constant, 273 * so we simply don't match on the main vendor id. 274 */ 275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 278 279 {0,} 280}; 281MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 282 283static struct { 284 const char str[ETH_GSTRING_LEN]; 285} ethtool_stats_keys[] = { 286 { "early_rx" }, 287 { "tx_buf_mapped" }, 288 { "tx_timeouts" }, 289 { "rx_lost_in_ring" }, 290}; 291 292/* The rest of these values should never change. */ 293 294/* Symbolic offsets to registers. */ 295enum RTL8139_registers { 296 MAC0 = 0, /* Ethernet hardware address. */ 297 MAR0 = 8, /* Multicast filter. */ 298 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 299 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 300 RxBuf = 0x30, 301 ChipCmd = 0x37, 302 RxBufPtr = 0x38, 303 RxBufAddr = 0x3A, 304 IntrMask = 0x3C, 305 IntrStatus = 0x3E, 306 TxConfig = 0x40, 307 RxConfig = 0x44, 308 Timer = 0x48, /* A general-purpose counter. */ 309 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 310 Cfg9346 = 0x50, 311 Config0 = 0x51, 312 Config1 = 0x52, 313 TimerInt = 0x54, 314 MediaStatus = 0x58, 315 Config3 = 0x59, 316 Config4 = 0x5A, /* absent on RTL-8139A */ 317 HltClk = 0x5B, 318 MultiIntr = 0x5C, 319 TxSummary = 0x60, 320 BasicModeCtrl = 0x62, 321 BasicModeStatus = 0x64, 322 NWayAdvert = 0x66, 323 NWayLPAR = 0x68, 324 NWayExpansion = 0x6A, 325 /* Undocumented registers, but required for proper operation. */ 326 FIFOTMS = 0x70, /* FIFO Control and test. */ 327 CSCR = 0x74, /* Chip Status and Configuration Register. */ 328 PARA78 = 0x78, 329 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 330 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 331 Config5 = 0xD8, /* absent on RTL-8139A */ 332}; 333 334enum ClearBitMasks { 335 MultiIntrClear = 0xF000, 336 ChipCmdClear = 0xE2, 337 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 338}; 339 340enum ChipCmdBits { 341 CmdReset = 0x10, 342 CmdRxEnb = 0x08, 343 CmdTxEnb = 0x04, 344 RxBufEmpty = 0x01, 345}; 346 347/* Interrupt register bits, using my own meaningful names. */ 348enum IntrStatusBits { 349 PCIErr = 0x8000, 350 PCSTimeout = 0x4000, 351 RxFIFOOver = 0x40, 352 RxUnderrun = 0x20, 353 RxOverflow = 0x10, 354 TxErr = 0x08, 355 TxOK = 0x04, 356 RxErr = 0x02, 357 RxOK = 0x01, 358 359 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 360}; 361 362enum TxStatusBits { 363 TxHostOwns = 0x2000, 364 TxUnderrun = 0x4000, 365 TxStatOK = 0x8000, 366 TxOutOfWindow = 0x20000000, 367 TxAborted = 0x40000000, 368 TxCarrierLost = 0x80000000, 369}; 370enum RxStatusBits { 371 RxMulticast = 0x8000, 372 RxPhysical = 0x4000, 373 RxBroadcast = 0x2000, 374 RxBadSymbol = 0x0020, 375 RxRunt = 0x0010, 376 RxTooLong = 0x0008, 377 RxCRCErr = 0x0004, 378 RxBadAlign = 0x0002, 379 RxStatusOK = 0x0001, 380}; 381 382/* Bits in RxConfig. */ 383enum rx_mode_bits { 384 AcceptErr = 0x20, 385 AcceptRunt = 0x10, 386 AcceptBroadcast = 0x08, 387 AcceptMulticast = 0x04, 388 AcceptMyPhys = 0x02, 389 AcceptAllPhys = 0x01, 390}; 391 392/* Bits in TxConfig. */ 393enum tx_config_bits { 394 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 395 TxIFGShift = 24, 396 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 397 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 398 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 399 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 400 401 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 402 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 403 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 404 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 405 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 406 407 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 408}; 409 410/* Bits in Config1 */ 411enum Config1Bits { 412 Cfg1_PM_Enable = 0x01, 413 Cfg1_VPD_Enable = 0x02, 414 Cfg1_PIO = 0x04, 415 Cfg1_MMIO = 0x08, 416 LWAKE = 0x10, /* not on 8139, 8139A */ 417 Cfg1_Driver_Load = 0x20, 418 Cfg1_LED0 = 0x40, 419 Cfg1_LED1 = 0x80, 420 SLEEP = (1 << 1), /* only on 8139, 8139A */ 421 PWRDN = (1 << 0), /* only on 8139, 8139A */ 422}; 423 424/* Bits in Config3 */ 425enum Config3Bits { 426 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 427 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 428 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 429 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 430 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 431 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 432 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 433 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 434}; 435 436/* Bits in Config4 */ 437enum Config4Bits { 438 LWPTN = (1 << 2), /* not on 8139, 8139A */ 439}; 440 441/* Bits in Config5 */ 442enum Config5Bits { 443 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 444 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 445 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 446 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 447 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 448 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 449 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 450}; 451 452enum RxConfigBits { 453 /* rx fifo threshold */ 454 RxCfgFIFOShift = 13, 455 RxCfgFIFONone = (7 << RxCfgFIFOShift), 456 457 /* Max DMA burst */ 458 RxCfgDMAShift = 8, 459 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 460 461 /* rx ring buffer length */ 462 RxCfgRcv8K = 0, 463 RxCfgRcv16K = (1 << 11), 464 RxCfgRcv32K = (1 << 12), 465 RxCfgRcv64K = (1 << 11) | (1 << 12), 466 467 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 468 RxNoWrap = (1 << 7), 469}; 470 471/* Twister tuning parameters from RealTek. 472 Completely undocumented, but required to tune bad links on some boards. */ 473enum CSCRBits { 474 CSCR_LinkOKBit = 0x0400, 475 CSCR_LinkChangeBit = 0x0800, 476 CSCR_LinkStatusBits = 0x0f000, 477 CSCR_LinkDownOffCmd = 0x003c0, 478 CSCR_LinkDownCmd = 0x0f3c0, 479}; 480 481enum Cfg9346Bits { 482 Cfg9346_Lock = 0x00, 483 Cfg9346_Unlock = 0xC0, 484}; 485 486typedef enum { 487 CH_8139 = 0, 488 CH_8139_K, 489 CH_8139A, 490 CH_8139A_G, 491 CH_8139B, 492 CH_8130, 493 CH_8139C, 494 CH_8100, 495 CH_8100B_8139D, 496 CH_8101, 497} chip_t; 498 499enum chip_flags { 500 HasHltClk = (1 << 0), 501 HasLWake = (1 << 1), 502}; 503 504#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 505 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 506#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 507 508/* directly indexed by chip_t, above */ 509static const struct { 510 const char *name; 511 u32 version; /* from RTL8139C/RTL8139D docs */ 512 u32 flags; 513} rtl_chip_info[] = { 514 { "RTL-8139", 515 HW_REVID(1, 0, 0, 0, 0, 0, 0), 516 HasHltClk, 517 }, 518 519 { "RTL-8139 rev K", 520 HW_REVID(1, 1, 0, 0, 0, 0, 0), 521 HasHltClk, 522 }, 523 524 { "RTL-8139A", 525 HW_REVID(1, 1, 1, 0, 0, 0, 0), 526 HasHltClk, /* XXX undocumented? */ 527 }, 528 529 { "RTL-8139A rev G", 530 HW_REVID(1, 1, 1, 0, 0, 1, 0), 531 HasHltClk, /* XXX undocumented? */ 532 }, 533 534 { "RTL-8139B", 535 HW_REVID(1, 1, 1, 1, 0, 0, 0), 536 HasLWake, 537 }, 538 539 { "RTL-8130", 540 HW_REVID(1, 1, 1, 1, 1, 0, 0), 541 HasLWake, 542 }, 543 544 { "RTL-8139C", 545 HW_REVID(1, 1, 1, 0, 1, 0, 0), 546 HasLWake, 547 }, 548 549 { "RTL-8100", 550 HW_REVID(1, 1, 1, 1, 0, 1, 0), 551 HasLWake, 552 }, 553 554 { "RTL-8100B/8139D", 555 HW_REVID(1, 1, 1, 0, 1, 0, 1), 556 HasHltClk /* XXX undocumented? */ 557 | HasLWake, 558 }, 559 560 { "RTL-8101", 561 HW_REVID(1, 1, 1, 0, 1, 1, 1), 562 HasLWake, 563 }, 564}; 565 566struct rtl_extra_stats { 567 unsigned long early_rx; 568 unsigned long tx_buf_mapped; 569 unsigned long tx_timeouts; 570 unsigned long rx_lost_in_ring; 571}; 572 573struct rtl8139_stats { 574 u64 packets; 575 u64 bytes; 576 struct u64_stats_sync syncp; 577}; 578 579struct rtl8139_private { 580 void __iomem *mmio_addr; 581 int drv_flags; 582 struct pci_dev *pci_dev; 583 u32 msg_enable; 584 struct napi_struct napi; 585 struct net_device *dev; 586 587 unsigned char *rx_ring; 588 unsigned int cur_rx; /* RX buf index of next pkt */ 589 struct rtl8139_stats rx_stats; 590 dma_addr_t rx_ring_dma; 591 592 unsigned int tx_flag; 593 unsigned long cur_tx; 594 unsigned long dirty_tx; 595 struct rtl8139_stats tx_stats; 596 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 597 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 598 dma_addr_t tx_bufs_dma; 599 600 signed char phys[4]; /* MII device addresses. */ 601 602 /* Twister tune state. */ 603 char twistie, twist_row, twist_col; 604 605 unsigned int watchdog_fired : 1; 606 unsigned int default_port : 4; /* Last dev->if_port value. */ 607 unsigned int have_thread : 1; 608 609 spinlock_t lock; 610 spinlock_t rx_lock; 611 612 chip_t chipset; 613 u32 rx_config; 614 struct rtl_extra_stats xstats; 615 616 struct delayed_work thread; 617 618 struct mii_if_info mii; 619 unsigned int regs_len; 620 unsigned long fifo_copy_timeout; 621}; 622 623MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 624MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 625MODULE_LICENSE("GPL"); 626MODULE_VERSION(DRV_VERSION); 627 628module_param(use_io, bool, 0); 629MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 630module_param(multicast_filter_limit, int, 0); 631module_param_array(media, int, NULL, 0); 632module_param_array(full_duplex, int, NULL, 0); 633module_param(debug, int, 0); 634MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 635MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 636MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 637MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 638 639static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 640static int rtl8139_open (struct net_device *dev); 641static int mdio_read (struct net_device *dev, int phy_id, int location); 642static void mdio_write (struct net_device *dev, int phy_id, int location, 643 int val); 644static void rtl8139_start_thread(struct rtl8139_private *tp); 645static void rtl8139_tx_timeout (struct net_device *dev, unsigned int txqueue); 646static void rtl8139_init_ring (struct net_device *dev); 647static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 648 struct net_device *dev); 649#ifdef CONFIG_NET_POLL_CONTROLLER 650static void rtl8139_poll_controller(struct net_device *dev); 651#endif 652static int rtl8139_set_mac_address(struct net_device *dev, void *p); 653static int rtl8139_poll(struct napi_struct *napi, int budget); 654static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 655static int rtl8139_close (struct net_device *dev); 656static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 657static void rtl8139_get_stats64(struct net_device *dev, 658 struct rtnl_link_stats64 *stats); 659static void rtl8139_set_rx_mode (struct net_device *dev); 660static void __set_rx_mode (struct net_device *dev); 661static void rtl8139_hw_start (struct net_device *dev); 662static void rtl8139_thread (struct work_struct *work); 663static void rtl8139_tx_timeout_task(struct work_struct *work); 664static const struct ethtool_ops rtl8139_ethtool_ops; 665 666/* write MMIO register, with flush */ 667/* Flush avoids rtl8139 bug w/ posted MMIO writes */ 668#define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 669#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 670#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 671 672/* write MMIO register */ 673#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 674#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 675#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 676 677/* read MMIO register */ 678#define RTL_R8(reg) ioread8 (ioaddr + (reg)) 679#define RTL_R16(reg) ioread16 (ioaddr + (reg)) 680#define RTL_R32(reg) ioread32 (ioaddr + (reg)) 681 682 683static const u16 rtl8139_intr_mask = 684 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 685 TxErr | TxOK | RxErr | RxOK; 686 687static const u16 rtl8139_norx_intr_mask = 688 PCIErr | PCSTimeout | RxUnderrun | 689 TxErr | TxOK | RxErr ; 690 691#if RX_BUF_IDX == 0 692static const unsigned int rtl8139_rx_config = 693 RxCfgRcv8K | RxNoWrap | 694 (RX_FIFO_THRESH << RxCfgFIFOShift) | 695 (RX_DMA_BURST << RxCfgDMAShift); 696#elif RX_BUF_IDX == 1 697static const unsigned int rtl8139_rx_config = 698 RxCfgRcv16K | RxNoWrap | 699 (RX_FIFO_THRESH << RxCfgFIFOShift) | 700 (RX_DMA_BURST << RxCfgDMAShift); 701#elif RX_BUF_IDX == 2 702static const unsigned int rtl8139_rx_config = 703 RxCfgRcv32K | RxNoWrap | 704 (RX_FIFO_THRESH << RxCfgFIFOShift) | 705 (RX_DMA_BURST << RxCfgDMAShift); 706#elif RX_BUF_IDX == 3 707static const unsigned int rtl8139_rx_config = 708 RxCfgRcv64K | 709 (RX_FIFO_THRESH << RxCfgFIFOShift) | 710 (RX_DMA_BURST << RxCfgDMAShift); 711#else 712#error "Invalid configuration for 8139_RXBUF_IDX" 713#endif 714 715static const unsigned int rtl8139_tx_config = 716 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 717 718static void __rtl8139_cleanup_dev (struct net_device *dev) 719{ 720 struct rtl8139_private *tp = netdev_priv(dev); 721 struct pci_dev *pdev; 722 723 assert (dev != NULL); 724 assert (tp->pci_dev != NULL); 725 pdev = tp->pci_dev; 726 727 if (tp->mmio_addr) 728 pci_iounmap (pdev, tp->mmio_addr); 729 730 /* it's ok to call this even if we have no regions to free */ 731 pci_release_regions (pdev); 732 733 free_netdev(dev); 734} 735 736 737static void rtl8139_chip_reset (void __iomem *ioaddr) 738{ 739 int i; 740 741 /* Soft reset the chip. */ 742 RTL_W8 (ChipCmd, CmdReset); 743 744 /* Check that the chip has finished the reset. */ 745 for (i = 1000; i > 0; i--) { 746 barrier(); 747 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 748 break; 749 udelay (10); 750 } 751} 752 753 754static struct net_device *rtl8139_init_board(struct pci_dev *pdev) 755{ 756 struct device *d = &pdev->dev; 757 void __iomem *ioaddr; 758 struct net_device *dev; 759 struct rtl8139_private *tp; 760 u8 tmp8; 761 int rc, disable_dev_on_err = 0; 762 unsigned int i, bar; 763 unsigned long io_len; 764 u32 version; 765 static const struct { 766 unsigned long mask; 767 char *type; 768 } res[] = { 769 { IORESOURCE_IO, "PIO" }, 770 { IORESOURCE_MEM, "MMIO" } 771 }; 772 773 assert (pdev != NULL); 774 775 /* dev and priv zeroed in alloc_etherdev */ 776 dev = alloc_etherdev (sizeof (*tp)); 777 if (dev == NULL) 778 return ERR_PTR(-ENOMEM); 779 780 SET_NETDEV_DEV(dev, &pdev->dev); 781 782 tp = netdev_priv(dev); 783 tp->pci_dev = pdev; 784 785 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 786 rc = pci_enable_device (pdev); 787 if (rc) 788 goto err_out; 789 790 disable_dev_on_err = 1; 791 rc = pci_request_regions (pdev, DRV_NAME); 792 if (rc) 793 goto err_out; 794 795 pci_set_master (pdev); 796 797 u64_stats_init(&tp->rx_stats.syncp); 798 u64_stats_init(&tp->tx_stats.syncp); 799 800retry: 801 /* PIO bar register comes first. */ 802 bar = !use_io; 803 804 io_len = pci_resource_len(pdev, bar); 805 806 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); 807 808 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { 809 dev_err(d, "region #%d not a %s resource, aborting\n", bar, 810 res[bar].type); 811 rc = -ENODEV; 812 goto err_out; 813 } 814 if (io_len < RTL_MIN_IO_SIZE) { 815 dev_err(d, "Invalid PCI %s region size(s), aborting\n", 816 res[bar].type); 817 rc = -ENODEV; 818 goto err_out; 819 } 820 821 ioaddr = pci_iomap(pdev, bar, 0); 822 if (!ioaddr) { 823 dev_err(d, "cannot map %s\n", res[bar].type); 824 if (!use_io) { 825 use_io = true; 826 goto retry; 827 } 828 rc = -ENODEV; 829 goto err_out; 830 } 831 tp->regs_len = io_len; 832 tp->mmio_addr = ioaddr; 833 834 /* Bring old chips out of low-power mode. */ 835 RTL_W8 (HltClk, 'R'); 836 837 /* check for missing/broken hardware */ 838 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 839 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 840 rc = -EIO; 841 goto err_out; 842 } 843 844 /* identify chip attached to board */ 845 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 846 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 847 if (version == rtl_chip_info[i].version) { 848 tp->chipset = i; 849 goto match; 850 } 851 852 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 853 i = 0; 854 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 855 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 856 tp->chipset = 0; 857 858match: 859 pr_debug("chipset id (%d) == index %d, '%s'\n", 860 version, i, rtl_chip_info[i].name); 861 862 if (tp->chipset >= CH_8139B) { 863 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 864 pr_debug("PCI PM wakeup\n"); 865 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 866 (tmp8 & LWAKE)) 867 new_tmp8 &= ~LWAKE; 868 new_tmp8 |= Cfg1_PM_Enable; 869 if (new_tmp8 != tmp8) { 870 RTL_W8 (Cfg9346, Cfg9346_Unlock); 871 RTL_W8 (Config1, tmp8); 872 RTL_W8 (Cfg9346, Cfg9346_Lock); 873 } 874 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 875 tmp8 = RTL_R8 (Config4); 876 if (tmp8 & LWPTN) { 877 RTL_W8 (Cfg9346, Cfg9346_Unlock); 878 RTL_W8 (Config4, tmp8 & ~LWPTN); 879 RTL_W8 (Cfg9346, Cfg9346_Lock); 880 } 881 } 882 } else { 883 pr_debug("Old chip wakeup\n"); 884 tmp8 = RTL_R8 (Config1); 885 tmp8 &= ~(SLEEP | PWRDN); 886 RTL_W8 (Config1, tmp8); 887 } 888 889 rtl8139_chip_reset (ioaddr); 890 891 return dev; 892 893err_out: 894 __rtl8139_cleanup_dev (dev); 895 if (disable_dev_on_err) 896 pci_disable_device (pdev); 897 return ERR_PTR(rc); 898} 899 900static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 901{ 902 struct rtl8139_private *tp = netdev_priv(dev); 903 unsigned long flags; 904 netdev_features_t changed = features ^ dev->features; 905 void __iomem *ioaddr = tp->mmio_addr; 906 907 if (!(changed & (NETIF_F_RXALL))) 908 return 0; 909 910 spin_lock_irqsave(&tp->lock, flags); 911 912 if (changed & NETIF_F_RXALL) { 913 int rx_mode = tp->rx_config; 914 if (features & NETIF_F_RXALL) 915 rx_mode |= (AcceptErr | AcceptRunt); 916 else 917 rx_mode &= ~(AcceptErr | AcceptRunt); 918 tp->rx_config = rtl8139_rx_config | rx_mode; 919 RTL_W32_F(RxConfig, tp->rx_config); 920 } 921 922 spin_unlock_irqrestore(&tp->lock, flags); 923 924 return 0; 925} 926 927static const struct net_device_ops rtl8139_netdev_ops = { 928 .ndo_open = rtl8139_open, 929 .ndo_stop = rtl8139_close, 930 .ndo_get_stats64 = rtl8139_get_stats64, 931 .ndo_validate_addr = eth_validate_addr, 932 .ndo_set_mac_address = rtl8139_set_mac_address, 933 .ndo_start_xmit = rtl8139_start_xmit, 934 .ndo_set_rx_mode = rtl8139_set_rx_mode, 935 .ndo_eth_ioctl = netdev_ioctl, 936 .ndo_tx_timeout = rtl8139_tx_timeout, 937#ifdef CONFIG_NET_POLL_CONTROLLER 938 .ndo_poll_controller = rtl8139_poll_controller, 939#endif 940 .ndo_set_features = rtl8139_set_features, 941}; 942 943static int rtl8139_init_one(struct pci_dev *pdev, 944 const struct pci_device_id *ent) 945{ 946 struct net_device *dev = NULL; 947 struct rtl8139_private *tp; 948 __le16 addr[ETH_ALEN / 2]; 949 int i, addr_len, option; 950 void __iomem *ioaddr; 951 static int board_idx = -1; 952 953 assert (pdev != NULL); 954 assert (ent != NULL); 955 956 board_idx++; 957 958 /* when we're built into the kernel, the driver version message 959 * is only printed if at least one 8139 board has been found 960 */ 961#ifndef MODULE 962 { 963 static int printed_version; 964 if (!printed_version++) 965 pr_info(RTL8139_DRIVER_NAME "\n"); 966 } 967#endif 968 969 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 970 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 971 dev_info(&pdev->dev, 972 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 973 pdev->vendor, pdev->device, pdev->revision); 974 return -ENODEV; 975 } 976 977 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 978 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 979 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 980 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 981 pr_info("OQO Model 2 detected. Forcing PIO\n"); 982 use_io = true; 983 } 984 985 dev = rtl8139_init_board (pdev); 986 if (IS_ERR(dev)) 987 return PTR_ERR(dev); 988 989 assert (dev != NULL); 990 tp = netdev_priv(dev); 991 tp->dev = dev; 992 993 ioaddr = tp->mmio_addr; 994 assert (ioaddr != NULL); 995 996 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 997 for (i = 0; i < 3; i++) 998 addr[i] = cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 999 eth_hw_addr_set(dev, (u8 *)addr); 1000 1001 /* The Rtl8139-specific entries in the device structure. */ 1002 dev->netdev_ops = &rtl8139_netdev_ops; 1003 dev->ethtool_ops = &rtl8139_ethtool_ops; 1004 dev->watchdog_timeo = TX_TIMEOUT; 1005 netif_napi_add(dev, &tp->napi, rtl8139_poll); 1006 1007 /* note: the hardware is not capable of sg/csum/highdma, however 1008 * through the use of skb_copy_and_csum_dev we enable these 1009 * features 1010 */ 1011 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 1012 dev->vlan_features = dev->features; 1013 1014 dev->hw_features |= NETIF_F_RXALL; 1015 dev->hw_features |= NETIF_F_RXFCS; 1016 1017 /* MTU range: 68 - 1770 */ 1018 dev->min_mtu = ETH_MIN_MTU; 1019 dev->max_mtu = MAX_ETH_DATA_SIZE; 1020 1021 /* tp zeroed and aligned in alloc_etherdev */ 1022 tp = netdev_priv(dev); 1023 1024 /* note: tp->chipset set in rtl8139_init_board */ 1025 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1026 tp->mmio_addr = ioaddr; 1027 tp->msg_enable = 1028 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1029 spin_lock_init (&tp->lock); 1030 spin_lock_init (&tp->rx_lock); 1031 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1032 tp->mii.dev = dev; 1033 tp->mii.mdio_read = mdio_read; 1034 tp->mii.mdio_write = mdio_write; 1035 tp->mii.phy_id_mask = 0x3f; 1036 tp->mii.reg_num_mask = 0x1f; 1037 1038 /* dev is fully set up and ready to use now */ 1039 pr_debug("about to register device named %s (%p)...\n", 1040 dev->name, dev); 1041 i = register_netdev (dev); 1042 if (i) goto err_out; 1043 1044 pci_set_drvdata (pdev, dev); 1045 1046 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n", 1047 board_info[ent->driver_data].name, 1048 ioaddr, dev->dev_addr, pdev->irq); 1049 1050 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1051 rtl_chip_info[tp->chipset].name); 1052 1053 /* Find the connected MII xcvrs. 1054 Doing this in open() would allow detecting external xcvrs later, but 1055 takes too much time. */ 1056#ifdef CONFIG_8139TOO_8129 1057 if (tp->drv_flags & HAS_MII_XCVR) { 1058 int phy, phy_idx = 0; 1059 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1060 int mii_status = mdio_read(dev, phy, 1); 1061 if (mii_status != 0xffff && mii_status != 0x0000) { 1062 u16 advertising = mdio_read(dev, phy, 4); 1063 tp->phys[phy_idx++] = phy; 1064 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1065 phy, mii_status, advertising); 1066 } 1067 } 1068 if (phy_idx == 0) { 1069 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1070 tp->phys[0] = 32; 1071 } 1072 } else 1073#endif 1074 tp->phys[0] = 32; 1075 tp->mii.phy_id = tp->phys[0]; 1076 1077 /* The lower four bits are the media type. */ 1078 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1079 if (option > 0) { 1080 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1081 tp->default_port = option & 0xFF; 1082 if (tp->default_port) 1083 tp->mii.force_media = 1; 1084 } 1085 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1086 tp->mii.full_duplex = full_duplex[board_idx]; 1087 if (tp->mii.full_duplex) { 1088 netdev_info(dev, "Media type forced to Full Duplex\n"); 1089 /* Changing the MII-advertised media because might prevent 1090 re-connection. */ 1091 tp->mii.force_media = 1; 1092 } 1093 if (tp->default_port) { 1094 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1095 (option & 0x20 ? 100 : 10), 1096 (option & 0x10 ? "full" : "half")); 1097 mdio_write(dev, tp->phys[0], 0, 1098 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1099 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1100 } 1101 1102 /* Put the chip into low-power mode. */ 1103 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1104 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1105 1106 return 0; 1107 1108err_out: 1109 __rtl8139_cleanup_dev (dev); 1110 pci_disable_device (pdev); 1111 return i; 1112} 1113 1114 1115static void rtl8139_remove_one(struct pci_dev *pdev) 1116{ 1117 struct net_device *dev = pci_get_drvdata (pdev); 1118 struct rtl8139_private *tp = netdev_priv(dev); 1119 1120 assert (dev != NULL); 1121 1122 cancel_delayed_work_sync(&tp->thread); 1123 1124 unregister_netdev (dev); 1125 1126 __rtl8139_cleanup_dev (dev); 1127 pci_disable_device (pdev); 1128} 1129 1130 1131/* Serial EEPROM section. */ 1132 1133/* EEPROM_Ctrl bits. */ 1134#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1135#define EE_CS 0x08 /* EEPROM chip select. */ 1136#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1137#define EE_WRITE_0 0x00 1138#define EE_WRITE_1 0x02 1139#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1140#define EE_ENB (0x80 | EE_CS) 1141 1142/* Delay between EEPROM clock transitions. 1143 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1144 */ 1145 1146#define eeprom_delay() (void)RTL_R8(Cfg9346) 1147 1148/* The EEPROM commands include the alway-set leading bit. */ 1149#define EE_WRITE_CMD (5) 1150#define EE_READ_CMD (6) 1151#define EE_ERASE_CMD (7) 1152 1153static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) 1154{ 1155 int i; 1156 unsigned retval = 0; 1157 int read_cmd = location | (EE_READ_CMD << addr_len); 1158 1159 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1160 RTL_W8 (Cfg9346, EE_ENB); 1161 eeprom_delay (); 1162 1163 /* Shift the read command bits out. */ 1164 for (i = 4 + addr_len; i >= 0; i--) { 1165 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1166 RTL_W8 (Cfg9346, EE_ENB | dataval); 1167 eeprom_delay (); 1168 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1169 eeprom_delay (); 1170 } 1171 RTL_W8 (Cfg9346, EE_ENB); 1172 eeprom_delay (); 1173 1174 for (i = 16; i > 0; i--) { 1175 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1176 eeprom_delay (); 1177 retval = 1178 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1179 0); 1180 RTL_W8 (Cfg9346, EE_ENB); 1181 eeprom_delay (); 1182 } 1183 1184 /* Terminate the EEPROM access. */ 1185 RTL_W8(Cfg9346, 0); 1186 eeprom_delay (); 1187 1188 return retval; 1189} 1190 1191/* MII serial management: mostly bogus for now. */ 1192/* Read and write the MII management registers using software-generated 1193 serial MDIO protocol. 1194 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1195 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1196 "overclocking" issues. */ 1197#define MDIO_DIR 0x80 1198#define MDIO_DATA_OUT 0x04 1199#define MDIO_DATA_IN 0x02 1200#define MDIO_CLK 0x01 1201#define MDIO_WRITE0 (MDIO_DIR) 1202#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1203 1204#define mdio_delay() RTL_R8(Config4) 1205 1206 1207static const char mii_2_8139_map[8] = { 1208 BasicModeCtrl, 1209 BasicModeStatus, 1210 0, 1211 0, 1212 NWayAdvert, 1213 NWayLPAR, 1214 NWayExpansion, 1215 0 1216}; 1217 1218 1219#ifdef CONFIG_8139TOO_8129 1220/* Syncronize the MII management interface by shifting 32 one bits out. */ 1221static void mdio_sync (void __iomem *ioaddr) 1222{ 1223 int i; 1224 1225 for (i = 32; i >= 0; i--) { 1226 RTL_W8 (Config4, MDIO_WRITE1); 1227 mdio_delay (); 1228 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1229 mdio_delay (); 1230 } 1231} 1232#endif 1233 1234static int mdio_read (struct net_device *dev, int phy_id, int location) 1235{ 1236 struct rtl8139_private *tp = netdev_priv(dev); 1237 int retval = 0; 1238#ifdef CONFIG_8139TOO_8129 1239 void __iomem *ioaddr = tp->mmio_addr; 1240 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1241 int i; 1242#endif 1243 1244 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1245 void __iomem *ioaddr = tp->mmio_addr; 1246 return location < 8 && mii_2_8139_map[location] ? 1247 RTL_R16 (mii_2_8139_map[location]) : 0; 1248 } 1249 1250#ifdef CONFIG_8139TOO_8129 1251 mdio_sync (ioaddr); 1252 /* Shift the read command bits out. */ 1253 for (i = 15; i >= 0; i--) { 1254 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1255 1256 RTL_W8 (Config4, MDIO_DIR | dataval); 1257 mdio_delay (); 1258 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1259 mdio_delay (); 1260 } 1261 1262 /* Read the two transition, 16 data, and wire-idle bits. */ 1263 for (i = 19; i > 0; i--) { 1264 RTL_W8 (Config4, 0); 1265 mdio_delay (); 1266 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1267 RTL_W8 (Config4, MDIO_CLK); 1268 mdio_delay (); 1269 } 1270#endif 1271 1272 return (retval >> 1) & 0xffff; 1273} 1274 1275 1276static void mdio_write (struct net_device *dev, int phy_id, int location, 1277 int value) 1278{ 1279 struct rtl8139_private *tp = netdev_priv(dev); 1280#ifdef CONFIG_8139TOO_8129 1281 void __iomem *ioaddr = tp->mmio_addr; 1282 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1283 int i; 1284#endif 1285 1286 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1287 void __iomem *ioaddr = tp->mmio_addr; 1288 if (location == 0) { 1289 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1290 RTL_W16 (BasicModeCtrl, value); 1291 RTL_W8 (Cfg9346, Cfg9346_Lock); 1292 } else if (location < 8 && mii_2_8139_map[location]) 1293 RTL_W16 (mii_2_8139_map[location], value); 1294 return; 1295 } 1296 1297#ifdef CONFIG_8139TOO_8129 1298 mdio_sync (ioaddr); 1299 1300 /* Shift the command bits out. */ 1301 for (i = 31; i >= 0; i--) { 1302 int dataval = 1303 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1304 RTL_W8 (Config4, dataval); 1305 mdio_delay (); 1306 RTL_W8 (Config4, dataval | MDIO_CLK); 1307 mdio_delay (); 1308 } 1309 /* Clear out extra bits. */ 1310 for (i = 2; i > 0; i--) { 1311 RTL_W8 (Config4, 0); 1312 mdio_delay (); 1313 RTL_W8 (Config4, MDIO_CLK); 1314 mdio_delay (); 1315 } 1316#endif 1317} 1318 1319 1320static int rtl8139_open (struct net_device *dev) 1321{ 1322 struct rtl8139_private *tp = netdev_priv(dev); 1323 void __iomem *ioaddr = tp->mmio_addr; 1324 const int irq = tp->pci_dev->irq; 1325 int retval; 1326 1327 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1328 if (retval) 1329 return retval; 1330 1331 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1332 &tp->tx_bufs_dma, GFP_KERNEL); 1333 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1334 &tp->rx_ring_dma, GFP_KERNEL); 1335 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1336 free_irq(irq, dev); 1337 1338 if (tp->tx_bufs) 1339 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1340 tp->tx_bufs, tp->tx_bufs_dma); 1341 if (tp->rx_ring) 1342 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1343 tp->rx_ring, tp->rx_ring_dma); 1344 1345 return -ENOMEM; 1346 1347 } 1348 1349 napi_enable(&tp->napi); 1350 1351 tp->mii.full_duplex = tp->mii.force_media; 1352 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1353 1354 rtl8139_init_ring (dev); 1355 rtl8139_hw_start (dev); 1356 netif_start_queue (dev); 1357 1358 netif_dbg(tp, ifup, dev, 1359 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1360 __func__, 1361 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1362 irq, RTL_R8 (MediaStatus), 1363 tp->mii.full_duplex ? "full" : "half"); 1364 1365 rtl8139_start_thread(tp); 1366 1367 return 0; 1368} 1369 1370 1371static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1372{ 1373 struct rtl8139_private *tp = netdev_priv(dev); 1374 1375 if (tp->phys[0] >= 0) { 1376 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1377 } 1378} 1379 1380/* Start the hardware at open or resume. */ 1381static void rtl8139_hw_start (struct net_device *dev) 1382{ 1383 struct rtl8139_private *tp = netdev_priv(dev); 1384 void __iomem *ioaddr = tp->mmio_addr; 1385 u32 i; 1386 u8 tmp; 1387 1388 /* Bring old chips out of low-power mode. */ 1389 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1390 RTL_W8 (HltClk, 'R'); 1391 1392 rtl8139_chip_reset (ioaddr); 1393 1394 /* unlock Config[01234] and BMCR register writes */ 1395 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1396 /* Restore our idea of the MAC address. */ 1397 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1398 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1399 1400 tp->cur_rx = 0; 1401 1402 /* init Rx ring buffer DMA address */ 1403 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1404 1405 /* Must enable Tx/Rx before setting transfer thresholds! */ 1406 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1407 1408 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1409 RTL_W32 (RxConfig, tp->rx_config); 1410 RTL_W32 (TxConfig, rtl8139_tx_config); 1411 1412 rtl_check_media (dev, 1); 1413 1414 if (tp->chipset >= CH_8139B) { 1415 /* Disable magic packet scanning, which is enabled 1416 * when PM is enabled in Config1. It can be reenabled 1417 * via ETHTOOL_SWOL if desired. */ 1418 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1419 } 1420 1421 netdev_dbg(dev, "init buffer addresses\n"); 1422 1423 /* Lock Config[01234] and BMCR register writes */ 1424 RTL_W8 (Cfg9346, Cfg9346_Lock); 1425 1426 /* init Tx buffer DMA addresses */ 1427 for (i = 0; i < NUM_TX_DESC; i++) 1428 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1429 1430 RTL_W32 (RxMissed, 0); 1431 1432 rtl8139_set_rx_mode (dev); 1433 1434 /* no early-rx interrupts */ 1435 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1436 1437 /* make sure RxTx has started */ 1438 tmp = RTL_R8 (ChipCmd); 1439 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1440 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1441 1442 /* Enable all known interrupts by setting the interrupt mask. */ 1443 RTL_W16 (IntrMask, rtl8139_intr_mask); 1444} 1445 1446 1447/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1448static void rtl8139_init_ring (struct net_device *dev) 1449{ 1450 struct rtl8139_private *tp = netdev_priv(dev); 1451 int i; 1452 1453 tp->cur_rx = 0; 1454 tp->cur_tx = 0; 1455 tp->dirty_tx = 0; 1456 1457 for (i = 0; i < NUM_TX_DESC; i++) 1458 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1459} 1460 1461 1462/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1463static int next_tick = 3 * HZ; 1464 1465#ifndef CONFIG_8139TOO_TUNE_TWISTER 1466static inline void rtl8139_tune_twister (struct net_device *dev, 1467 struct rtl8139_private *tp) {} 1468#else 1469enum TwisterParamVals { 1470 PARA78_default = 0x78fa8388, 1471 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1472 PARA7c_xxx = 0xcb38de43, 1473}; 1474 1475static const unsigned long param[4][4] = { 1476 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1477 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1478 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1479 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1480}; 1481 1482static void rtl8139_tune_twister (struct net_device *dev, 1483 struct rtl8139_private *tp) 1484{ 1485 int linkcase; 1486 void __iomem *ioaddr = tp->mmio_addr; 1487 1488 /* This is a complicated state machine to configure the "twister" for 1489 impedance/echos based on the cable length. 1490 All of this is magic and undocumented. 1491 */ 1492 switch (tp->twistie) { 1493 case 1: 1494 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1495 /* We have link beat, let us tune the twister. */ 1496 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1497 tp->twistie = 2; /* Change to state 2. */ 1498 next_tick = HZ / 10; 1499 } else { 1500 /* Just put in some reasonable defaults for when beat returns. */ 1501 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1502 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1503 RTL_W32 (PARA78, PARA78_default); 1504 RTL_W32 (PARA7c, PARA7c_default); 1505 tp->twistie = 0; /* Bail from future actions. */ 1506 } 1507 break; 1508 case 2: 1509 /* Read how long it took to hear the echo. */ 1510 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1511 if (linkcase == 0x7000) 1512 tp->twist_row = 3; 1513 else if (linkcase == 0x3000) 1514 tp->twist_row = 2; 1515 else if (linkcase == 0x1000) 1516 tp->twist_row = 1; 1517 else 1518 tp->twist_row = 0; 1519 tp->twist_col = 0; 1520 tp->twistie = 3; /* Change to state 2. */ 1521 next_tick = HZ / 10; 1522 break; 1523 case 3: 1524 /* Put out four tuning parameters, one per 100msec. */ 1525 if (tp->twist_col == 0) 1526 RTL_W16 (FIFOTMS, 0); 1527 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1528 [(int) tp->twist_col]); 1529 next_tick = HZ / 10; 1530 if (++tp->twist_col >= 4) { 1531 /* For short cables we are done. 1532 For long cables (row == 3) check for mistune. */ 1533 tp->twistie = 1534 (tp->twist_row == 3) ? 4 : 0; 1535 } 1536 break; 1537 case 4: 1538 /* Special case for long cables: check for mistune. */ 1539 if ((RTL_R16 (CSCR) & 1540 CSCR_LinkStatusBits) == 0x7000) { 1541 tp->twistie = 0; 1542 break; 1543 } else { 1544 RTL_W32 (PARA7c, 0xfb38de03); 1545 tp->twistie = 5; 1546 next_tick = HZ / 10; 1547 } 1548 break; 1549 case 5: 1550 /* Retune for shorter cable (column 2). */ 1551 RTL_W32 (FIFOTMS, 0x20); 1552 RTL_W32 (PARA78, PARA78_default); 1553 RTL_W32 (PARA7c, PARA7c_default); 1554 RTL_W32 (FIFOTMS, 0x00); 1555 tp->twist_row = 2; 1556 tp->twist_col = 0; 1557 tp->twistie = 3; 1558 next_tick = HZ / 10; 1559 break; 1560 1561 default: 1562 /* do nothing */ 1563 break; 1564 } 1565} 1566#endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1567 1568static inline void rtl8139_thread_iter (struct net_device *dev, 1569 struct rtl8139_private *tp, 1570 void __iomem *ioaddr) 1571{ 1572 int mii_lpa; 1573 1574 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1575 1576 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1577 int duplex = ((mii_lpa & LPA_100FULL) || 1578 (mii_lpa & 0x01C0) == 0x0040); 1579 if (tp->mii.full_duplex != duplex) { 1580 tp->mii.full_duplex = duplex; 1581 1582 if (mii_lpa) { 1583 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1584 tp->mii.full_duplex ? "full" : "half", 1585 tp->phys[0], mii_lpa); 1586 } else { 1587 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1588 } 1589#if 0 1590 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1591 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1592 RTL_W8 (Cfg9346, Cfg9346_Lock); 1593#endif 1594 } 1595 } 1596 1597 next_tick = HZ * 60; 1598 1599 rtl8139_tune_twister (dev, tp); 1600 1601 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1602 RTL_R16(NWayLPAR)); 1603 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1604 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1605 netdev_dbg(dev, "Chip config %02x %02x\n", 1606 RTL_R8(Config0), RTL_R8(Config1)); 1607} 1608 1609static void rtl8139_thread (struct work_struct *work) 1610{ 1611 struct rtl8139_private *tp = 1612 container_of(work, struct rtl8139_private, thread.work); 1613 struct net_device *dev = tp->mii.dev; 1614 unsigned long thr_delay = next_tick; 1615 1616 rtnl_lock(); 1617 1618 if (!netif_running(dev)) 1619 goto out_unlock; 1620 1621 if (tp->watchdog_fired) { 1622 tp->watchdog_fired = 0; 1623 rtl8139_tx_timeout_task(work); 1624 } else 1625 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1626 1627 if (tp->have_thread) 1628 schedule_delayed_work(&tp->thread, thr_delay); 1629out_unlock: 1630 rtnl_unlock (); 1631} 1632 1633static void rtl8139_start_thread(struct rtl8139_private *tp) 1634{ 1635 tp->twistie = 0; 1636 if (tp->chipset == CH_8139_K) 1637 tp->twistie = 1; 1638 else if (tp->drv_flags & HAS_LNK_CHNG) 1639 return; 1640 1641 tp->have_thread = 1; 1642 tp->watchdog_fired = 0; 1643 1644 schedule_delayed_work(&tp->thread, next_tick); 1645} 1646 1647static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1648{ 1649 tp->cur_tx = 0; 1650 tp->dirty_tx = 0; 1651 1652 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1653} 1654 1655static void rtl8139_tx_timeout_task (struct work_struct *work) 1656{ 1657 struct rtl8139_private *tp = 1658 container_of(work, struct rtl8139_private, thread.work); 1659 struct net_device *dev = tp->mii.dev; 1660 void __iomem *ioaddr = tp->mmio_addr; 1661 int i; 1662 u8 tmp8; 1663 1664 napi_disable(&tp->napi); 1665 netif_stop_queue(dev); 1666 synchronize_rcu(); 1667 1668 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1669 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1670 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1671 /* Emit info to figure out what went wrong. */ 1672 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1673 tp->cur_tx, tp->dirty_tx); 1674 for (i = 0; i < NUM_TX_DESC; i++) 1675 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1676 i, RTL_R32(TxStatus0 + (i * 4)), 1677 i == tp->dirty_tx % NUM_TX_DESC ? 1678 " (queue head)" : ""); 1679 1680 tp->xstats.tx_timeouts++; 1681 1682 /* disable Tx ASAP, if not already */ 1683 tmp8 = RTL_R8 (ChipCmd); 1684 if (tmp8 & CmdTxEnb) 1685 RTL_W8 (ChipCmd, CmdRxEnb); 1686 1687 spin_lock_bh(&tp->rx_lock); 1688 /* Disable interrupts by clearing the interrupt mask. */ 1689 RTL_W16 (IntrMask, 0x0000); 1690 1691 /* Stop a shared interrupt from scavenging while we are. */ 1692 spin_lock_irq(&tp->lock); 1693 rtl8139_tx_clear (tp); 1694 spin_unlock_irq(&tp->lock); 1695 1696 /* ...and finally, reset everything */ 1697 napi_enable(&tp->napi); 1698 rtl8139_hw_start(dev); 1699 netif_wake_queue(dev); 1700 1701 spin_unlock_bh(&tp->rx_lock); 1702} 1703 1704static void rtl8139_tx_timeout(struct net_device *dev, unsigned int txqueue) 1705{ 1706 struct rtl8139_private *tp = netdev_priv(dev); 1707 1708 tp->watchdog_fired = 1; 1709 if (!tp->have_thread) { 1710 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1711 schedule_delayed_work(&tp->thread, next_tick); 1712 } 1713} 1714 1715static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1716 struct net_device *dev) 1717{ 1718 struct rtl8139_private *tp = netdev_priv(dev); 1719 void __iomem *ioaddr = tp->mmio_addr; 1720 unsigned int entry; 1721 unsigned int len = skb->len; 1722 unsigned long flags; 1723 1724 /* Calculate the next Tx descriptor entry. */ 1725 entry = tp->cur_tx % NUM_TX_DESC; 1726 1727 /* Note: the chip doesn't have auto-pad! */ 1728 if (likely(len < TX_BUF_SIZE)) { 1729 if (len < ETH_ZLEN) 1730 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1731 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1732 dev_kfree_skb_any(skb); 1733 } else { 1734 dev_kfree_skb_any(skb); 1735 dev->stats.tx_dropped++; 1736 return NETDEV_TX_OK; 1737 } 1738 1739 spin_lock_irqsave(&tp->lock, flags); 1740 /* 1741 * Writing to TxStatus triggers a DMA transfer of the data 1742 * copied to tp->tx_buf[entry] above. Use a memory barrier 1743 * to make sure that the device sees the updated data. 1744 */ 1745 wmb(); 1746 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1747 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1748 1749 tp->cur_tx++; 1750 1751 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1752 netif_stop_queue (dev); 1753 spin_unlock_irqrestore(&tp->lock, flags); 1754 1755 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1756 len, entry); 1757 1758 return NETDEV_TX_OK; 1759} 1760 1761 1762static void rtl8139_tx_interrupt (struct net_device *dev, 1763 struct rtl8139_private *tp, 1764 void __iomem *ioaddr) 1765{ 1766 unsigned long dirty_tx, tx_left; 1767 1768 assert (dev != NULL); 1769 assert (ioaddr != NULL); 1770 1771 dirty_tx = tp->dirty_tx; 1772 tx_left = tp->cur_tx - dirty_tx; 1773 while (tx_left > 0) { 1774 int entry = dirty_tx % NUM_TX_DESC; 1775 int txstatus; 1776 1777 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1778 1779 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1780 break; /* It still hasn't been Txed */ 1781 1782 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1783 if (txstatus & (TxOutOfWindow | TxAborted)) { 1784 /* There was an major error, log it. */ 1785 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1786 txstatus); 1787 dev->stats.tx_errors++; 1788 if (txstatus & TxAborted) { 1789 dev->stats.tx_aborted_errors++; 1790 RTL_W32 (TxConfig, TxClearAbt); 1791 RTL_W16 (IntrStatus, TxErr); 1792 wmb(); 1793 } 1794 if (txstatus & TxCarrierLost) 1795 dev->stats.tx_carrier_errors++; 1796 if (txstatus & TxOutOfWindow) 1797 dev->stats.tx_window_errors++; 1798 } else { 1799 if (txstatus & TxUnderrun) { 1800 /* Add 64 to the Tx FIFO threshold. */ 1801 if (tp->tx_flag < 0x00300000) 1802 tp->tx_flag += 0x00020000; 1803 dev->stats.tx_fifo_errors++; 1804 } 1805 dev->stats.collisions += (txstatus >> 24) & 15; 1806 u64_stats_update_begin(&tp->tx_stats.syncp); 1807 tp->tx_stats.packets++; 1808 tp->tx_stats.bytes += txstatus & 0x7ff; 1809 u64_stats_update_end(&tp->tx_stats.syncp); 1810 } 1811 1812 dirty_tx++; 1813 tx_left--; 1814 } 1815 1816#ifndef RTL8139_NDEBUG 1817 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1818 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1819 dirty_tx, tp->cur_tx); 1820 dirty_tx += NUM_TX_DESC; 1821 } 1822#endif /* RTL8139_NDEBUG */ 1823 1824 /* only wake the queue if we did work, and the queue is stopped */ 1825 if (tp->dirty_tx != dirty_tx) { 1826 tp->dirty_tx = dirty_tx; 1827 mb(); 1828 netif_wake_queue (dev); 1829 } 1830} 1831 1832 1833/* TODO: clean this up! Rx reset need not be this intensive */ 1834static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1835 struct rtl8139_private *tp, void __iomem *ioaddr) 1836{ 1837 u8 tmp8; 1838#ifdef CONFIG_8139_OLD_RX_RESET 1839 int tmp_work; 1840#endif 1841 1842 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1843 rx_status); 1844 dev->stats.rx_errors++; 1845 if (!(rx_status & RxStatusOK)) { 1846 if (rx_status & RxTooLong) { 1847 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1848 rx_status); 1849 /* A.C.: The chip hangs here. */ 1850 } 1851 if (rx_status & (RxBadSymbol | RxBadAlign)) 1852 dev->stats.rx_frame_errors++; 1853 if (rx_status & (RxRunt | RxTooLong)) 1854 dev->stats.rx_length_errors++; 1855 if (rx_status & RxCRCErr) 1856 dev->stats.rx_crc_errors++; 1857 } else { 1858 tp->xstats.rx_lost_in_ring++; 1859 } 1860 1861#ifndef CONFIG_8139_OLD_RX_RESET 1862 tmp8 = RTL_R8 (ChipCmd); 1863 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1864 RTL_W8 (ChipCmd, tmp8); 1865 RTL_W32 (RxConfig, tp->rx_config); 1866 tp->cur_rx = 0; 1867#else 1868 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1869 1870 /* disable receive */ 1871 RTL_W8_F (ChipCmd, CmdTxEnb); 1872 tmp_work = 200; 1873 while (--tmp_work > 0) { 1874 udelay(1); 1875 tmp8 = RTL_R8 (ChipCmd); 1876 if (!(tmp8 & CmdRxEnb)) 1877 break; 1878 } 1879 if (tmp_work <= 0) 1880 netdev_warn(dev, "rx stop wait too long\n"); 1881 /* restart receive */ 1882 tmp_work = 200; 1883 while (--tmp_work > 0) { 1884 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1885 udelay(1); 1886 tmp8 = RTL_R8 (ChipCmd); 1887 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1888 break; 1889 } 1890 if (tmp_work <= 0) 1891 netdev_warn(dev, "tx/rx enable wait too long\n"); 1892 1893 /* and reinitialize all rx related registers */ 1894 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1895 /* Must enable Tx/Rx before setting transfer thresholds! */ 1896 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1897 1898 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1899 RTL_W32 (RxConfig, tp->rx_config); 1900 tp->cur_rx = 0; 1901 1902 netdev_dbg(dev, "init buffer addresses\n"); 1903 1904 /* Lock Config[01234] and BMCR register writes */ 1905 RTL_W8 (Cfg9346, Cfg9346_Lock); 1906 1907 /* init Rx ring buffer DMA address */ 1908 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1909 1910 /* A.C.: Reset the multicast list. */ 1911 __set_rx_mode (dev); 1912#endif 1913} 1914 1915#if RX_BUF_IDX == 3 1916static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1917 u32 offset, unsigned int size) 1918{ 1919 u32 left = RX_BUF_LEN - offset; 1920 1921 if (size > left) { 1922 skb_copy_to_linear_data(skb, ring + offset, left); 1923 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1924 } else 1925 skb_copy_to_linear_data(skb, ring + offset, size); 1926} 1927#endif 1928 1929static void rtl8139_isr_ack(struct rtl8139_private *tp) 1930{ 1931 void __iomem *ioaddr = tp->mmio_addr; 1932 u16 status; 1933 1934 status = RTL_R16 (IntrStatus) & RxAckBits; 1935 1936 /* Clear out errors and receive interrupts */ 1937 if (likely(status != 0)) { 1938 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1939 tp->dev->stats.rx_errors++; 1940 if (status & RxFIFOOver) 1941 tp->dev->stats.rx_fifo_errors++; 1942 } 1943 RTL_W16_F (IntrStatus, RxAckBits); 1944 } 1945} 1946 1947static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1948 int budget) 1949{ 1950 void __iomem *ioaddr = tp->mmio_addr; 1951 int received = 0; 1952 unsigned char *rx_ring = tp->rx_ring; 1953 unsigned int cur_rx = tp->cur_rx; 1954 unsigned int rx_size = 0; 1955 1956 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1957 __func__, (u16)cur_rx, 1958 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1959 1960 while (netif_running(dev) && received < budget && 1961 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1962 u32 ring_offset = cur_rx % RX_BUF_LEN; 1963 u32 rx_status; 1964 unsigned int pkt_size; 1965 struct sk_buff *skb; 1966 1967 rmb(); 1968 1969 /* read size+status of next frame from DMA ring buffer */ 1970 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1971 rx_size = rx_status >> 16; 1972 if (likely(!(dev->features & NETIF_F_RXFCS))) 1973 pkt_size = rx_size - 4; 1974 else 1975 pkt_size = rx_size; 1976 1977 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1978 __func__, rx_status, rx_size, cur_rx); 1979#if RTL8139_DEBUG > 2 1980 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1981 DUMP_PREFIX_OFFSET, 16, 1, 1982 &rx_ring[ring_offset], 70, true); 1983#endif 1984 1985 /* Packet copy from FIFO still in progress. 1986 * Theoretically, this should never happen 1987 * since EarlyRx is disabled. 1988 */ 1989 if (unlikely(rx_size == 0xfff0)) { 1990 if (!tp->fifo_copy_timeout) 1991 tp->fifo_copy_timeout = jiffies + 2; 1992 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1993 netdev_dbg(dev, "hung FIFO. Reset\n"); 1994 rx_size = 0; 1995 goto no_early_rx; 1996 } 1997 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 1998 tp->xstats.early_rx++; 1999 break; 2000 } 2001 2002no_early_rx: 2003 tp->fifo_copy_timeout = 0; 2004 2005 /* If Rx err or invalid rx_size/rx_status received 2006 * (which happens if we get lost in the ring), 2007 * Rx process gets reset, so we abort any further 2008 * Rx processing. 2009 */ 2010 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 2011 (rx_size < 8) || 2012 (!(rx_status & RxStatusOK)))) { 2013 if ((dev->features & NETIF_F_RXALL) && 2014 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2015 (rx_size >= 8) && 2016 (!(rx_status & RxStatusOK))) { 2017 /* Length is at least mostly OK, but pkt has 2018 * error. I'm hoping we can handle some of these 2019 * errors without resetting the chip. --Ben 2020 */ 2021 dev->stats.rx_errors++; 2022 if (rx_status & RxCRCErr) { 2023 dev->stats.rx_crc_errors++; 2024 goto keep_pkt; 2025 } 2026 if (rx_status & RxRunt) { 2027 dev->stats.rx_length_errors++; 2028 goto keep_pkt; 2029 } 2030 } 2031 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2032 received = -1; 2033 goto out; 2034 } 2035 2036keep_pkt: 2037 /* Malloc up new buffer, compatible with net-2e. */ 2038 /* Omit the four octet CRC from the length. */ 2039 2040 skb = napi_alloc_skb(&tp->napi, pkt_size); 2041 if (likely(skb)) { 2042#if RX_BUF_IDX == 3 2043 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2044#else 2045 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2046#endif 2047 skb_put (skb, pkt_size); 2048 2049 skb->protocol = eth_type_trans (skb, dev); 2050 2051 u64_stats_update_begin(&tp->rx_stats.syncp); 2052 tp->rx_stats.packets++; 2053 tp->rx_stats.bytes += pkt_size; 2054 u64_stats_update_end(&tp->rx_stats.syncp); 2055 2056 netif_receive_skb (skb); 2057 } else { 2058 dev->stats.rx_dropped++; 2059 } 2060 received++; 2061 2062 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2063 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2064 2065 rtl8139_isr_ack(tp); 2066 } 2067 2068 if (unlikely(!received || rx_size == 0xfff0)) 2069 rtl8139_isr_ack(tp); 2070 2071 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2072 __func__, cur_rx, 2073 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2074 2075 tp->cur_rx = cur_rx; 2076 2077 /* 2078 * The receive buffer should be mostly empty. 2079 * Tell NAPI to reenable the Rx irq. 2080 */ 2081 if (tp->fifo_copy_timeout) 2082 received = budget; 2083 2084out: 2085 return received; 2086} 2087 2088 2089static void rtl8139_weird_interrupt (struct net_device *dev, 2090 struct rtl8139_private *tp, 2091 void __iomem *ioaddr, 2092 int status, int link_changed) 2093{ 2094 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2095 2096 assert (dev != NULL); 2097 assert (tp != NULL); 2098 assert (ioaddr != NULL); 2099 2100 /* Update the error count. */ 2101 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2102 RTL_W32 (RxMissed, 0); 2103 2104 if ((status & RxUnderrun) && link_changed && 2105 (tp->drv_flags & HAS_LNK_CHNG)) { 2106 rtl_check_media(dev, 0); 2107 status &= ~RxUnderrun; 2108 } 2109 2110 if (status & (RxUnderrun | RxErr)) 2111 dev->stats.rx_errors++; 2112 2113 if (status & PCSTimeout) 2114 dev->stats.rx_length_errors++; 2115 if (status & RxUnderrun) 2116 dev->stats.rx_fifo_errors++; 2117 if (status & PCIErr) { 2118 u16 pci_cmd_status; 2119 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2120 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2121 2122 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2123 } 2124} 2125 2126static int rtl8139_poll(struct napi_struct *napi, int budget) 2127{ 2128 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2129 struct net_device *dev = tp->dev; 2130 void __iomem *ioaddr = tp->mmio_addr; 2131 int work_done; 2132 2133 spin_lock(&tp->rx_lock); 2134 work_done = 0; 2135 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2136 work_done += rtl8139_rx(dev, tp, budget); 2137 2138 if (work_done < budget) { 2139 unsigned long flags; 2140 2141 spin_lock_irqsave(&tp->lock, flags); 2142 if (napi_complete_done(napi, work_done)) 2143 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2144 spin_unlock_irqrestore(&tp->lock, flags); 2145 } 2146 spin_unlock(&tp->rx_lock); 2147 2148 return work_done; 2149} 2150 2151/* The interrupt handler does all of the Rx thread work and cleans up 2152 after the Tx thread. */ 2153static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2154{ 2155 struct net_device *dev = (struct net_device *) dev_instance; 2156 struct rtl8139_private *tp = netdev_priv(dev); 2157 void __iomem *ioaddr = tp->mmio_addr; 2158 u16 status, ackstat; 2159 int link_changed = 0; /* avoid bogus "uninit" warning */ 2160 int handled = 0; 2161 2162 spin_lock (&tp->lock); 2163 status = RTL_R16 (IntrStatus); 2164 2165 /* shared irq? */ 2166 if (unlikely((status & rtl8139_intr_mask) == 0)) 2167 goto out; 2168 2169 handled = 1; 2170 2171 /* h/w no longer present (hotplug?) or major error, bail */ 2172 if (unlikely(status == 0xFFFF)) 2173 goto out; 2174 2175 /* close possible race's with dev_close */ 2176 if (unlikely(!netif_running(dev))) { 2177 RTL_W16 (IntrMask, 0); 2178 goto out; 2179 } 2180 2181 /* Acknowledge all of the current interrupt sources ASAP, but 2182 an first get an additional status bit from CSCR. */ 2183 if (unlikely(status & RxUnderrun)) 2184 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2185 2186 ackstat = status & ~(RxAckBits | TxErr); 2187 if (ackstat) 2188 RTL_W16 (IntrStatus, ackstat); 2189 2190 /* Receive packets are processed by poll routine. 2191 If not running start it now. */ 2192 if (status & RxAckBits){ 2193 if (napi_schedule_prep(&tp->napi)) { 2194 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2195 __napi_schedule(&tp->napi); 2196 } 2197 } 2198 2199 /* Check uncommon events with one test. */ 2200 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2201 rtl8139_weird_interrupt (dev, tp, ioaddr, 2202 status, link_changed); 2203 2204 if (status & (TxOK | TxErr)) { 2205 rtl8139_tx_interrupt (dev, tp, ioaddr); 2206 if (status & TxErr) 2207 RTL_W16 (IntrStatus, TxErr); 2208 } 2209 out: 2210 spin_unlock (&tp->lock); 2211 2212 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2213 RTL_R16(IntrStatus)); 2214 return IRQ_RETVAL(handled); 2215} 2216 2217#ifdef CONFIG_NET_POLL_CONTROLLER 2218/* 2219 * Polling receive - used by netconsole and other diagnostic tools 2220 * to allow network i/o with interrupts disabled. 2221 */ 2222static void rtl8139_poll_controller(struct net_device *dev) 2223{ 2224 struct rtl8139_private *tp = netdev_priv(dev); 2225 const int irq = tp->pci_dev->irq; 2226 2227 disable_irq_nosync(irq); 2228 rtl8139_interrupt(irq, dev); 2229 enable_irq(irq); 2230} 2231#endif 2232 2233static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2234{ 2235 struct rtl8139_private *tp = netdev_priv(dev); 2236 void __iomem *ioaddr = tp->mmio_addr; 2237 struct sockaddr *addr = p; 2238 2239 if (!is_valid_ether_addr(addr->sa_data)) 2240 return -EADDRNOTAVAIL; 2241 2242 eth_hw_addr_set(dev, addr->sa_data); 2243 2244 spin_lock_irq(&tp->lock); 2245 2246 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2247 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2248 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2249 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2250 2251 spin_unlock_irq(&tp->lock); 2252 2253 return 0; 2254} 2255 2256static int rtl8139_close (struct net_device *dev) 2257{ 2258 struct rtl8139_private *tp = netdev_priv(dev); 2259 void __iomem *ioaddr = tp->mmio_addr; 2260 unsigned long flags; 2261 2262 netif_stop_queue(dev); 2263 napi_disable(&tp->napi); 2264 2265 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2266 RTL_R16(IntrStatus)); 2267 2268 spin_lock_irqsave (&tp->lock, flags); 2269 2270 /* Stop the chip's Tx and Rx DMA processes. */ 2271 RTL_W8 (ChipCmd, 0); 2272 2273 /* Disable interrupts by clearing the interrupt mask. */ 2274 RTL_W16 (IntrMask, 0); 2275 2276 /* Update the error counts. */ 2277 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2278 RTL_W32 (RxMissed, 0); 2279 2280 spin_unlock_irqrestore (&tp->lock, flags); 2281 2282 free_irq(tp->pci_dev->irq, dev); 2283 2284 rtl8139_tx_clear (tp); 2285 2286 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2287 tp->rx_ring, tp->rx_ring_dma); 2288 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2289 tp->tx_bufs, tp->tx_bufs_dma); 2290 tp->rx_ring = NULL; 2291 tp->tx_bufs = NULL; 2292 2293 /* Green! Put the chip in low-power mode. */ 2294 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2295 2296 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2297 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2298 2299 return 0; 2300} 2301 2302 2303/* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2304 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2305 other threads or interrupts aren't messing with the 8139. */ 2306static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2307{ 2308 struct rtl8139_private *tp = netdev_priv(dev); 2309 void __iomem *ioaddr = tp->mmio_addr; 2310 2311 spin_lock_irq(&tp->lock); 2312 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2313 u8 cfg3 = RTL_R8 (Config3); 2314 u8 cfg5 = RTL_R8 (Config5); 2315 2316 wol->supported = WAKE_PHY | WAKE_MAGIC 2317 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2318 2319 wol->wolopts = 0; 2320 if (cfg3 & Cfg3_LinkUp) 2321 wol->wolopts |= WAKE_PHY; 2322 if (cfg3 & Cfg3_Magic) 2323 wol->wolopts |= WAKE_MAGIC; 2324 /* (KON)FIXME: See how netdev_set_wol() handles the 2325 following constants. */ 2326 if (cfg5 & Cfg5_UWF) 2327 wol->wolopts |= WAKE_UCAST; 2328 if (cfg5 & Cfg5_MWF) 2329 wol->wolopts |= WAKE_MCAST; 2330 if (cfg5 & Cfg5_BWF) 2331 wol->wolopts |= WAKE_BCAST; 2332 } 2333 spin_unlock_irq(&tp->lock); 2334} 2335 2336 2337/* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2338 that wol points to kernel memory and other threads or interrupts 2339 aren't messing with the 8139. */ 2340static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2341{ 2342 struct rtl8139_private *tp = netdev_priv(dev); 2343 void __iomem *ioaddr = tp->mmio_addr; 2344 u32 support; 2345 u8 cfg3, cfg5; 2346 2347 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2348 ? (WAKE_PHY | WAKE_MAGIC 2349 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2350 : 0); 2351 if (wol->wolopts & ~support) 2352 return -EINVAL; 2353 2354 spin_lock_irq(&tp->lock); 2355 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2356 if (wol->wolopts & WAKE_PHY) 2357 cfg3 |= Cfg3_LinkUp; 2358 if (wol->wolopts & WAKE_MAGIC) 2359 cfg3 |= Cfg3_Magic; 2360 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2361 RTL_W8 (Config3, cfg3); 2362 RTL_W8 (Cfg9346, Cfg9346_Lock); 2363 2364 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2365 /* (KON)FIXME: These are untested. We may have to set the 2366 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2367 documentation. */ 2368 if (wol->wolopts & WAKE_UCAST) 2369 cfg5 |= Cfg5_UWF; 2370 if (wol->wolopts & WAKE_MCAST) 2371 cfg5 |= Cfg5_MWF; 2372 if (wol->wolopts & WAKE_BCAST) 2373 cfg5 |= Cfg5_BWF; 2374 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2375 spin_unlock_irq(&tp->lock); 2376 2377 return 0; 2378} 2379 2380static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2381{ 2382 struct rtl8139_private *tp = netdev_priv(dev); 2383 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2384 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 2385 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2386} 2387 2388static int rtl8139_get_link_ksettings(struct net_device *dev, 2389 struct ethtool_link_ksettings *cmd) 2390{ 2391 struct rtl8139_private *tp = netdev_priv(dev); 2392 spin_lock_irq(&tp->lock); 2393 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 2394 spin_unlock_irq(&tp->lock); 2395 return 0; 2396} 2397 2398static int rtl8139_set_link_ksettings(struct net_device *dev, 2399 const struct ethtool_link_ksettings *cmd) 2400{ 2401 struct rtl8139_private *tp = netdev_priv(dev); 2402 int rc; 2403 spin_lock_irq(&tp->lock); 2404 rc = mii_ethtool_set_link_ksettings(&tp->mii, cmd); 2405 spin_unlock_irq(&tp->lock); 2406 return rc; 2407} 2408 2409static int rtl8139_nway_reset(struct net_device *dev) 2410{ 2411 struct rtl8139_private *tp = netdev_priv(dev); 2412 return mii_nway_restart(&tp->mii); 2413} 2414 2415static u32 rtl8139_get_link(struct net_device *dev) 2416{ 2417 struct rtl8139_private *tp = netdev_priv(dev); 2418 return mii_link_ok(&tp->mii); 2419} 2420 2421static u32 rtl8139_get_msglevel(struct net_device *dev) 2422{ 2423 struct rtl8139_private *tp = netdev_priv(dev); 2424 return tp->msg_enable; 2425} 2426 2427static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2428{ 2429 struct rtl8139_private *tp = netdev_priv(dev); 2430 tp->msg_enable = datum; 2431} 2432 2433static int rtl8139_get_regs_len(struct net_device *dev) 2434{ 2435 struct rtl8139_private *tp; 2436 /* TODO: we are too slack to do reg dumping for pio, for now */ 2437 if (use_io) 2438 return 0; 2439 tp = netdev_priv(dev); 2440 return tp->regs_len; 2441} 2442 2443static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2444{ 2445 struct rtl8139_private *tp; 2446 2447 /* TODO: we are too slack to do reg dumping for pio, for now */ 2448 if (use_io) 2449 return; 2450 tp = netdev_priv(dev); 2451 2452 regs->version = RTL_REGS_VER; 2453 2454 spin_lock_irq(&tp->lock); 2455 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2456 spin_unlock_irq(&tp->lock); 2457} 2458 2459static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2460{ 2461 switch (sset) { 2462 case ETH_SS_STATS: 2463 return RTL_NUM_STATS; 2464 default: 2465 return -EOPNOTSUPP; 2466 } 2467} 2468 2469static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2470{ 2471 struct rtl8139_private *tp = netdev_priv(dev); 2472 2473 data[0] = tp->xstats.early_rx; 2474 data[1] = tp->xstats.tx_buf_mapped; 2475 data[2] = tp->xstats.tx_timeouts; 2476 data[3] = tp->xstats.rx_lost_in_ring; 2477} 2478 2479static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2480{ 2481 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2482} 2483 2484static const struct ethtool_ops rtl8139_ethtool_ops = { 2485 .get_drvinfo = rtl8139_get_drvinfo, 2486 .get_regs_len = rtl8139_get_regs_len, 2487 .get_regs = rtl8139_get_regs, 2488 .nway_reset = rtl8139_nway_reset, 2489 .get_link = rtl8139_get_link, 2490 .get_msglevel = rtl8139_get_msglevel, 2491 .set_msglevel = rtl8139_set_msglevel, 2492 .get_wol = rtl8139_get_wol, 2493 .set_wol = rtl8139_set_wol, 2494 .get_strings = rtl8139_get_strings, 2495 .get_sset_count = rtl8139_get_sset_count, 2496 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2497 .get_link_ksettings = rtl8139_get_link_ksettings, 2498 .set_link_ksettings = rtl8139_set_link_ksettings, 2499}; 2500 2501static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2502{ 2503 struct rtl8139_private *tp = netdev_priv(dev); 2504 int rc; 2505 2506 if (!netif_running(dev)) 2507 return -EINVAL; 2508 2509 spin_lock_irq(&tp->lock); 2510 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2511 spin_unlock_irq(&tp->lock); 2512 2513 return rc; 2514} 2515 2516 2517static void 2518rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2519{ 2520 struct rtl8139_private *tp = netdev_priv(dev); 2521 void __iomem *ioaddr = tp->mmio_addr; 2522 unsigned long flags; 2523 unsigned int start; 2524 2525 if (netif_running(dev)) { 2526 spin_lock_irqsave (&tp->lock, flags); 2527 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2528 RTL_W32 (RxMissed, 0); 2529 spin_unlock_irqrestore (&tp->lock, flags); 2530 } 2531 2532 netdev_stats_to_stats64(stats, &dev->stats); 2533 2534 do { 2535 start = u64_stats_fetch_begin(&tp->rx_stats.syncp); 2536 stats->rx_packets = tp->rx_stats.packets; 2537 stats->rx_bytes = tp->rx_stats.bytes; 2538 } while (u64_stats_fetch_retry(&tp->rx_stats.syncp, start)); 2539 2540 do { 2541 start = u64_stats_fetch_begin(&tp->tx_stats.syncp); 2542 stats->tx_packets = tp->tx_stats.packets; 2543 stats->tx_bytes = tp->tx_stats.bytes; 2544 } while (u64_stats_fetch_retry(&tp->tx_stats.syncp, start)); 2545} 2546 2547/* Set or clear the multicast filter for this adaptor. 2548 This routine is not state sensitive and need not be SMP locked. */ 2549 2550static void __set_rx_mode (struct net_device *dev) 2551{ 2552 struct rtl8139_private *tp = netdev_priv(dev); 2553 void __iomem *ioaddr = tp->mmio_addr; 2554 u32 mc_filter[2]; /* Multicast hash filter */ 2555 int rx_mode; 2556 u32 tmp; 2557 2558 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2559 dev->flags, RTL_R32(RxConfig)); 2560 2561 /* Note: do not reorder, GCC is clever about common statements. */ 2562 if (dev->flags & IFF_PROMISC) { 2563 rx_mode = 2564 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2565 AcceptAllPhys; 2566 mc_filter[1] = mc_filter[0] = 0xffffffff; 2567 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2568 (dev->flags & IFF_ALLMULTI)) { 2569 /* Too many to filter perfectly -- accept all multicasts. */ 2570 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2571 mc_filter[1] = mc_filter[0] = 0xffffffff; 2572 } else { 2573 struct netdev_hw_addr *ha; 2574 rx_mode = AcceptBroadcast | AcceptMyPhys; 2575 mc_filter[1] = mc_filter[0] = 0; 2576 netdev_for_each_mc_addr(ha, dev) { 2577 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2578 2579 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2580 rx_mode |= AcceptMulticast; 2581 } 2582 } 2583 2584 if (dev->features & NETIF_F_RXALL) 2585 rx_mode |= (AcceptErr | AcceptRunt); 2586 2587 /* We can safely update without stopping the chip. */ 2588 tmp = rtl8139_rx_config | rx_mode; 2589 if (tp->rx_config != tmp) { 2590 RTL_W32_F (RxConfig, tmp); 2591 tp->rx_config = tmp; 2592 } 2593 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2594 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2595} 2596 2597static void rtl8139_set_rx_mode (struct net_device *dev) 2598{ 2599 unsigned long flags; 2600 struct rtl8139_private *tp = netdev_priv(dev); 2601 2602 spin_lock_irqsave (&tp->lock, flags); 2603 __set_rx_mode(dev); 2604 spin_unlock_irqrestore (&tp->lock, flags); 2605} 2606 2607static int __maybe_unused rtl8139_suspend(struct device *device) 2608{ 2609 struct net_device *dev = dev_get_drvdata(device); 2610 struct rtl8139_private *tp = netdev_priv(dev); 2611 void __iomem *ioaddr = tp->mmio_addr; 2612 unsigned long flags; 2613 2614 if (!netif_running (dev)) 2615 return 0; 2616 2617 netif_device_detach (dev); 2618 2619 spin_lock_irqsave (&tp->lock, flags); 2620 2621 /* Disable interrupts, stop Tx and Rx. */ 2622 RTL_W16 (IntrMask, 0); 2623 RTL_W8 (ChipCmd, 0); 2624 2625 /* Update the error counts. */ 2626 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2627 RTL_W32 (RxMissed, 0); 2628 2629 spin_unlock_irqrestore (&tp->lock, flags); 2630 2631 return 0; 2632} 2633 2634static int __maybe_unused rtl8139_resume(struct device *device) 2635{ 2636 struct net_device *dev = dev_get_drvdata(device); 2637 2638 if (!netif_running (dev)) 2639 return 0; 2640 2641 rtl8139_init_ring (dev); 2642 rtl8139_hw_start (dev); 2643 netif_device_attach (dev); 2644 return 0; 2645} 2646 2647static SIMPLE_DEV_PM_OPS(rtl8139_pm_ops, rtl8139_suspend, rtl8139_resume); 2648 2649static struct pci_driver rtl8139_pci_driver = { 2650 .name = DRV_NAME, 2651 .id_table = rtl8139_pci_tbl, 2652 .probe = rtl8139_init_one, 2653 .remove = rtl8139_remove_one, 2654 .driver.pm = &rtl8139_pm_ops, 2655}; 2656 2657 2658static int __init rtl8139_init_module (void) 2659{ 2660 /* when we're a module, we always print a version message, 2661 * even if no 8139 board is found. 2662 */ 2663#ifdef MODULE 2664 pr_info(RTL8139_DRIVER_NAME "\n"); 2665#endif 2666 2667 return pci_register_driver(&rtl8139_pci_driver); 2668} 2669 2670 2671static void __exit rtl8139_cleanup_module (void) 2672{ 2673 pci_unregister_driver (&rtl8139_pci_driver); 2674} 2675 2676 2677module_init(rtl8139_init_module); 2678module_exit(rtl8139_cleanup_module); 2679