Searched refs:block_id (Results 1 - 25 of 71) sorted by relevance

123

/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h31 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
32 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
33 #define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
34 #define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
35 #define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id)
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H A Dcvmx-stxx-defs.h31 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id)
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H A Dcvmx-pcsxx-defs.h31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) argument
37 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
40 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
42 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
44 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) argument
53 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
56 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
58 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
60 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) *
63 CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) argument
79 CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) argument
95 CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) argument
111 CVMX_PCSXX_INT_EN_REG(unsigned long block_id) argument
127 CVMX_PCSXX_INT_REG(unsigned long block_id) argument
143 CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) argument
159 CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) argument
175 CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) argument
191 CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) argument
207 CVMX_PCSXX_STATUS1_REG(unsigned long block_id) argument
223 CVMX_PCSXX_STATUS2_REG(unsigned long block_id) argument
239 CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) argument
255 CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) argument
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H A Dcvmx-asxx-defs.h31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
32 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
33 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
36 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SE
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H A Dcvmx-srxx-defs.h31 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
34 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id)
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H A Dcvmx-pcsx-defs.h31 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) argument
35 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
38 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
42 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
44 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
46 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
49 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) argument
53 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
56 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
60 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) *
67 CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) argument
85 CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) argument
103 CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) argument
121 CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) argument
139 CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) argument
157 CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) argument
175 CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) argument
193 CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) argument
211 CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) argument
229 CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) argument
247 CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) argument
265 CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) argument
283 CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) argument
301 CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) argument
319 CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) argument
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H A Dcvmx-spxx-defs.h31 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id)
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H A Dcvmx-pemx-defs.h31 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id)
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H A Dcvmx-l2c-defs.h36 #define CVMX_L2C_ERR_TDTX(block_id) \
37 (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
38 #define CVMX_L2C_ERR_TTGX(block_id) \
39 (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
54 #define CVMX_L2C_TADX_PFCX(offset, block_id) \
56 ((block_id) & 7) * 0x8000ull) * 8)
57 #define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \
58 ((block_id) & 3) * 0x40000ull)
59 #define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \
60 ((block_id)
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H A Dcvmx-lmcx-defs.h31 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
32 #define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
33 #define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
34 #define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
35 #define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id)
57 CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id) argument
76 CVMX_LMCX_ECC_SYND(unsigned long block_id) argument
98 CVMX_LMCX_FADR(unsigned long block_id) argument
129 CVMX_LMCX_NXM(unsigned long block_id) argument
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H A Dcvmx-sriox-defs.h31 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id)
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H A Dcvmx-pescx-defs.h31 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id)
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H A Dcvmx-gmxx-defs.h31 static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) argument
35 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
37 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
40 static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) argument
44 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
46 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
49 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) argument
53 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
55 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
57 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) *
60 CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) argument
71 CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) argument
82 CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) argument
93 CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) argument
104 CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) argument
115 CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) argument
126 CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) argument
137 CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) argument
148 CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) argument
162 CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) argument
173 CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) argument
184 CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) argument
197 CVMX_GMXX_RX_PRTS(unsigned long block_id) argument
206 CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) argument
215 CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) argument
226 CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) argument
238 CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) argument
249 CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) argument
260 CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) argument
271 CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) argument
282 CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) argument
293 CVMX_GMXX_TX_INT_EN(unsigned long block_id) argument
302 CVMX_GMXX_TX_INT_REG(unsigned long block_id) argument
311 CVMX_GMXX_TX_OVR_BP(unsigned long block_id) argument
320 CVMX_GMXX_TX_PRTS(unsigned long block_id) argument
332 CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) argument
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H A Dcvmx-pciercx-defs.h33 #define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
34 #define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
35 #define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
36 #define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
37 #define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
38 #define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
39 #define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
40 #define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
41 #define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
42 #define CVMX_PCIERCX_CFG034(block_id) (
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H A Dcvmx-uctlx-defs.h31 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
32 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
33 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
34 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
35 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
36 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
37 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
38 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
39 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
40 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SE
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/linux-master/drivers/pci/controller/
H A Dpci-hyperv-intf.c22 unsigned int block_id, unsigned int *bytes_returned)
27 return hvpci_block_ops.read_block(dev, buf, buf_len, block_id,
33 unsigned int block_id)
38 return hvpci_block_ops.write_block(dev, buf, len, block_id);
21 hyperv_read_cfg_blk(struct pci_dev *dev, void *buf, unsigned int buf_len, unsigned int block_id, unsigned int *bytes_returned) argument
32 hyperv_write_cfg_blk(struct pci_dev *dev, void *buf, unsigned int len, unsigned int block_id) argument
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dhv.c13 int block_id; local
18 block_id = offset / HV_CONFIG_BLOCK_SIZE_MAX;
22 HV_CONFIG_BLOCK_SIZE_MAX, block_id,
25 HV_CONFIG_BLOCK_SIZE_MAX, block_id);
/linux-master/drivers/net/ethernet/mscc/
H A Docelot_flower.c149 int block_id; local
151 block_id = ocelot_chain_to_block(chain, true);
152 if (block_id < 0)
155 if (block_id == VCAP_IS2) {
250 filter->block_id = ocelot_chain_to_block(chain, ingress);
251 if (filter->block_id < 0) {
255 if (filter->block_id == VCAP_IS1 || filter->block_id == VCAP_IS2)
257 if (filter->block_id == VCAP_IS2)
266 if (filter->block_id !
874 int block_id, ret; local
942 int block_id; local
980 int block_id, ret; local
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H A Docelot_vcap.c854 const struct vcap_props *vcap = &ocelot->vcap[filter->block_id];
859 if (filter->block_id == VCAP_ES0)
878 if (filter->block_id == VCAP_IS1)
880 if (filter->block_id == VCAP_IS2)
882 if (filter->block_id == VCAP_ES0)
962 if (filter->block_id == VCAP_IS2 && filter->action.mirror_ena) {
969 if (filter->block_id == VCAP_IS2 && filter->action.police_ena) {
983 if (filter->block_id == VCAP_IS2 && filter->action.police_ena)
986 if (filter->block_id == VCAP_IS2 && filter->action.mirror_ena)
1141 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];
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/linux-master/drivers/base/
H A Dmemory.c639 static struct memory_block *find_memory_block_by_id(unsigned long block_id) argument
643 mem = xa_load(&memory_blocks, block_id);
654 unsigned long block_id = memory_block_id(section_nr); local
656 return find_memory_block_by_id(block_id);
778 static int add_memory_block(unsigned long block_id, unsigned long state, argument
785 mem = find_memory_block_by_id(block_id);
794 mem->start_section_nr = block_id * sections_per_block;
839 static int add_hotplug_memory_block(unsigned long block_id, argument
843 return add_memory_block(block_id, MEM_OFFLINE, altmap, group);
877 unsigned long block_id; local
914 unsigned long block_id; local
1013 unsigned long block_id; local
1232 const unsigned long block_id = pfn_to_block_id(pfn); local
1241 const unsigned long block_id = pfn_to_block_id(pfn); local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dta_ras_if.h120 enum ta_ras_block block_id; member in struct:ta_ras_enable_features_input
125 enum ta_ras_block block_id; member in struct:ta_ras_disable_features_input
130 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx member in struct:ta_ras_trigger_error_input
/linux-master/drivers/accel/habanalabs/common/
H A Dsecurity.h148 * @block_id: block (ASIC specific definition can be dcore/hdcore)
149 * @major: major block index within block_id
154 int (*fn)(struct hl_device *hdev, u32 block_id, u32 major, u32 minor,
/linux-master/drivers/net/ethernet/marvell/prestera/
H A Dprestera_hw.h234 int prestera_hw_counter_trigger(struct prestera_switch *sw, u32 block_id);
240 u32 client, u32 *block_id, u32 *offset,
243 u32 block_id);
244 int prestera_hw_counter_clear(struct prestera_switch *sw, u32 block_id,
/linux-master/drivers/block/drbd/
H A Ddrbd_protocol.h95 * (except block_id and barrier fields.
147 u64 block_id; /* to identify the request in protocol B&C */ member in struct:p_data
172 u64 block_id; member in struct:p_block_ack
179 u64 block_id; member in struct:p_block_req
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_debug.c294 enum block_id sem_block_id;
1023 enum block_id block_id)
1028 return dbg_block + block_id;
1033 enum block_id
1034 block_id)
1040 block_id * MAX_CHIP_IDS + dev_data->chip_id;
1407 blk = qed_get_dbg_block_per_chip(p_hwfn, (enum block_id)blk_id);
1500 enum block_id block_id,
1022 get_dbg_block(struct qed_hwfn *p_hwfn, enum block_id block_id) argument
1031 qed_get_dbg_block_per_chip(struct qed_hwfn *p_hwfn, enum block_id block_id) argument
1498 qed_bus_config_dbg_line(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, enum block_id block_id, u8 line_id, u8 enable_mask, u8 right_shift, u8 force_valid_mask, u8 force_frame_mask) argument
1526 u32 block_id; local
1595 qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, enum block_id block_id, u8 mem_group_id) argument
1711 u32 block_id; local
1763 qed_get_block_attn_data(struct qed_hwfn *p_hwfn, enum block_id block_id, enum dbg_attn_type attn_type) argument
1775 qed_get_block_attn_regs(struct qed_hwfn *p_hwfn, enum block_id block_id, enum dbg_attn_type attn_type, u8 *num_attn_regs) argument
1795 u32 block_id, sts_clr_address; local
2426 u32 block_id, offset = 0, stall_regs_offset; local
3425 u32 block_id, line_id, offset = 0, addr, len; local
3782 u32 block_id; local
3886 u32 block_id = local
5713 qed_dbg_read_attn(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, enum block_id block_id, enum dbg_attn_type attn_type, bool clear_status, struct dbg_attn_block_result *results) argument
6463 qed_dbg_get_block_name(struct qed_hwfn *p_hwfn, enum block_id block_id) argument
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