1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT.  See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRXX_DEFS_H__
29#define __CVMX_SRXX_DEFS_H__
30
31#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
32#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
33#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
34#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
35#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
36#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
37
38union cvmx_srxx_com_ctl {
39	uint64_t u64;
40	struct cvmx_srxx_com_ctl_s {
41#ifdef __BIG_ENDIAN_BITFIELD
42		uint64_t reserved_8_63:56;
43		uint64_t prts:4;
44		uint64_t st_en:1;
45		uint64_t reserved_1_2:2;
46		uint64_t inf_en:1;
47#else
48		uint64_t inf_en:1;
49		uint64_t reserved_1_2:2;
50		uint64_t st_en:1;
51		uint64_t prts:4;
52		uint64_t reserved_8_63:56;
53#endif
54	} s;
55};
56
57union cvmx_srxx_ign_rx_full {
58	uint64_t u64;
59	struct cvmx_srxx_ign_rx_full_s {
60#ifdef __BIG_ENDIAN_BITFIELD
61		uint64_t reserved_16_63:48;
62		uint64_t ignore:16;
63#else
64		uint64_t ignore:16;
65		uint64_t reserved_16_63:48;
66#endif
67	} s;
68};
69
70union cvmx_srxx_spi4_calx {
71	uint64_t u64;
72	struct cvmx_srxx_spi4_calx_s {
73#ifdef __BIG_ENDIAN_BITFIELD
74		uint64_t reserved_17_63:47;
75		uint64_t oddpar:1;
76		uint64_t prt3:4;
77		uint64_t prt2:4;
78		uint64_t prt1:4;
79		uint64_t prt0:4;
80#else
81		uint64_t prt0:4;
82		uint64_t prt1:4;
83		uint64_t prt2:4;
84		uint64_t prt3:4;
85		uint64_t oddpar:1;
86		uint64_t reserved_17_63:47;
87#endif
88	} s;
89};
90
91union cvmx_srxx_spi4_stat {
92	uint64_t u64;
93	struct cvmx_srxx_spi4_stat_s {
94#ifdef __BIG_ENDIAN_BITFIELD
95		uint64_t reserved_16_63:48;
96		uint64_t m:8;
97		uint64_t reserved_7_7:1;
98		uint64_t len:7;
99#else
100		uint64_t len:7;
101		uint64_t reserved_7_7:1;
102		uint64_t m:8;
103		uint64_t reserved_16_63:48;
104#endif
105	} s;
106};
107
108union cvmx_srxx_sw_tick_ctl {
109	uint64_t u64;
110	struct cvmx_srxx_sw_tick_ctl_s {
111#ifdef __BIG_ENDIAN_BITFIELD
112		uint64_t reserved_14_63:50;
113		uint64_t eop:1;
114		uint64_t sop:1;
115		uint64_t mod:4;
116		uint64_t opc:4;
117		uint64_t adr:4;
118#else
119		uint64_t adr:4;
120		uint64_t opc:4;
121		uint64_t mod:4;
122		uint64_t sop:1;
123		uint64_t eop:1;
124		uint64_t reserved_14_63:50;
125#endif
126	} s;
127};
128
129union cvmx_srxx_sw_tick_dat {
130	uint64_t u64;
131	struct cvmx_srxx_sw_tick_dat_s {
132#ifdef __BIG_ENDIAN_BITFIELD
133		uint64_t dat:64;
134#else
135		uint64_t dat:64;
136#endif
137	} s;
138};
139
140#endif
141