1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_SRIOX_DEFS_H__ 29#define __CVMX_SRIOX_DEFS_H__ 30 31#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) 32#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) 33#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) 34#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) 35#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) 36#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) 37#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) 38#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 39#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 40#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) 41#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) 42#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) 43#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) 44#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) 45#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) 46#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) 47#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) 48#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) 49#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) 50#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) 51#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) 52#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) 53#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) 54#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) 55#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) 56#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 57#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 58#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 59#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 60#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 61#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) 62#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 63#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 64#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) 65#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) 66#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) 67#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) 68#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) 69#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) 70#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) 71#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) 72#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) 73#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) 74#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) 75#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) 76#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) 77#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) 78 79union cvmx_sriox_acc_ctrl { 80 uint64_t u64; 81 struct cvmx_sriox_acc_ctrl_s { 82#ifdef __BIG_ENDIAN_BITFIELD 83 uint64_t reserved_7_63:57; 84 uint64_t deny_adr2:1; 85 uint64_t deny_adr1:1; 86 uint64_t deny_adr0:1; 87 uint64_t reserved_3_3:1; 88 uint64_t deny_bar2:1; 89 uint64_t deny_bar1:1; 90 uint64_t deny_bar0:1; 91#else 92 uint64_t deny_bar0:1; 93 uint64_t deny_bar1:1; 94 uint64_t deny_bar2:1; 95 uint64_t reserved_3_3:1; 96 uint64_t deny_adr0:1; 97 uint64_t deny_adr1:1; 98 uint64_t deny_adr2:1; 99 uint64_t reserved_7_63:57; 100#endif 101 } s; 102 struct cvmx_sriox_acc_ctrl_cn63xx { 103#ifdef __BIG_ENDIAN_BITFIELD 104 uint64_t reserved_3_63:61; 105 uint64_t deny_bar2:1; 106 uint64_t deny_bar1:1; 107 uint64_t deny_bar0:1; 108#else 109 uint64_t deny_bar0:1; 110 uint64_t deny_bar1:1; 111 uint64_t deny_bar2:1; 112 uint64_t reserved_3_63:61; 113#endif 114 } cn63xx; 115}; 116 117union cvmx_sriox_asmbly_id { 118 uint64_t u64; 119 struct cvmx_sriox_asmbly_id_s { 120#ifdef __BIG_ENDIAN_BITFIELD 121 uint64_t reserved_32_63:32; 122 uint64_t assy_id:16; 123 uint64_t assy_ven:16; 124#else 125 uint64_t assy_ven:16; 126 uint64_t assy_id:16; 127 uint64_t reserved_32_63:32; 128#endif 129 } s; 130}; 131 132union cvmx_sriox_asmbly_info { 133 uint64_t u64; 134 struct cvmx_sriox_asmbly_info_s { 135#ifdef __BIG_ENDIAN_BITFIELD 136 uint64_t reserved_32_63:32; 137 uint64_t assy_rev:16; 138 uint64_t reserved_0_15:16; 139#else 140 uint64_t reserved_0_15:16; 141 uint64_t assy_rev:16; 142 uint64_t reserved_32_63:32; 143#endif 144 } s; 145}; 146 147union cvmx_sriox_bell_resp_ctrl { 148 uint64_t u64; 149 struct cvmx_sriox_bell_resp_ctrl_s { 150#ifdef __BIG_ENDIAN_BITFIELD 151 uint64_t reserved_6_63:58; 152 uint64_t rp1_sid:1; 153 uint64_t rp0_sid:2; 154 uint64_t rp1_pid:1; 155 uint64_t rp0_pid:2; 156#else 157 uint64_t rp0_pid:2; 158 uint64_t rp1_pid:1; 159 uint64_t rp0_sid:2; 160 uint64_t rp1_sid:1; 161 uint64_t reserved_6_63:58; 162#endif 163 } s; 164}; 165 166union cvmx_sriox_bist_status { 167 uint64_t u64; 168 struct cvmx_sriox_bist_status_s { 169#ifdef __BIG_ENDIAN_BITFIELD 170 uint64_t reserved_45_63:19; 171 uint64_t lram:1; 172 uint64_t mram:2; 173 uint64_t cram:2; 174 uint64_t bell:2; 175 uint64_t otag:2; 176 uint64_t itag:1; 177 uint64_t ofree:1; 178 uint64_t rtn:2; 179 uint64_t obulk:4; 180 uint64_t optrs:4; 181 uint64_t oarb2:2; 182 uint64_t rxbuf2:2; 183 uint64_t oarb:2; 184 uint64_t ispf:1; 185 uint64_t ospf:1; 186 uint64_t txbuf:2; 187 uint64_t rxbuf:2; 188 uint64_t imsg:5; 189 uint64_t omsg:7; 190#else 191 uint64_t omsg:7; 192 uint64_t imsg:5; 193 uint64_t rxbuf:2; 194 uint64_t txbuf:2; 195 uint64_t ospf:1; 196 uint64_t ispf:1; 197 uint64_t oarb:2; 198 uint64_t rxbuf2:2; 199 uint64_t oarb2:2; 200 uint64_t optrs:4; 201 uint64_t obulk:4; 202 uint64_t rtn:2; 203 uint64_t ofree:1; 204 uint64_t itag:1; 205 uint64_t otag:2; 206 uint64_t bell:2; 207 uint64_t cram:2; 208 uint64_t mram:2; 209 uint64_t lram:1; 210 uint64_t reserved_45_63:19; 211#endif 212 } s; 213 struct cvmx_sriox_bist_status_cn63xx { 214#ifdef __BIG_ENDIAN_BITFIELD 215 uint64_t reserved_44_63:20; 216 uint64_t mram:2; 217 uint64_t cram:2; 218 uint64_t bell:2; 219 uint64_t otag:2; 220 uint64_t itag:1; 221 uint64_t ofree:1; 222 uint64_t rtn:2; 223 uint64_t obulk:4; 224 uint64_t optrs:4; 225 uint64_t oarb2:2; 226 uint64_t rxbuf2:2; 227 uint64_t oarb:2; 228 uint64_t ispf:1; 229 uint64_t ospf:1; 230 uint64_t txbuf:2; 231 uint64_t rxbuf:2; 232 uint64_t imsg:5; 233 uint64_t omsg:7; 234#else 235 uint64_t omsg:7; 236 uint64_t imsg:5; 237 uint64_t rxbuf:2; 238 uint64_t txbuf:2; 239 uint64_t ospf:1; 240 uint64_t ispf:1; 241 uint64_t oarb:2; 242 uint64_t rxbuf2:2; 243 uint64_t oarb2:2; 244 uint64_t optrs:4; 245 uint64_t obulk:4; 246 uint64_t rtn:2; 247 uint64_t ofree:1; 248 uint64_t itag:1; 249 uint64_t otag:2; 250 uint64_t bell:2; 251 uint64_t cram:2; 252 uint64_t mram:2; 253 uint64_t reserved_44_63:20; 254#endif 255 } cn63xx; 256 struct cvmx_sriox_bist_status_cn63xxp1 { 257#ifdef __BIG_ENDIAN_BITFIELD 258 uint64_t reserved_44_63:20; 259 uint64_t mram:2; 260 uint64_t cram:2; 261 uint64_t bell:2; 262 uint64_t otag:2; 263 uint64_t itag:1; 264 uint64_t ofree:1; 265 uint64_t rtn:2; 266 uint64_t obulk:4; 267 uint64_t optrs:4; 268 uint64_t reserved_20_23:4; 269 uint64_t oarb:2; 270 uint64_t ispf:1; 271 uint64_t ospf:1; 272 uint64_t txbuf:2; 273 uint64_t rxbuf:2; 274 uint64_t imsg:5; 275 uint64_t omsg:7; 276#else 277 uint64_t omsg:7; 278 uint64_t imsg:5; 279 uint64_t rxbuf:2; 280 uint64_t txbuf:2; 281 uint64_t ospf:1; 282 uint64_t ispf:1; 283 uint64_t oarb:2; 284 uint64_t reserved_20_23:4; 285 uint64_t optrs:4; 286 uint64_t obulk:4; 287 uint64_t rtn:2; 288 uint64_t ofree:1; 289 uint64_t itag:1; 290 uint64_t otag:2; 291 uint64_t bell:2; 292 uint64_t cram:2; 293 uint64_t mram:2; 294 uint64_t reserved_44_63:20; 295#endif 296 } cn63xxp1; 297}; 298 299union cvmx_sriox_imsg_ctrl { 300 uint64_t u64; 301 struct cvmx_sriox_imsg_ctrl_s { 302#ifdef __BIG_ENDIAN_BITFIELD 303 uint64_t reserved_32_63:32; 304 uint64_t to_mode:1; 305 uint64_t reserved_30_30:1; 306 uint64_t rsp_thr:6; 307 uint64_t reserved_22_23:2; 308 uint64_t rp1_sid:1; 309 uint64_t rp0_sid:2; 310 uint64_t rp1_pid:1; 311 uint64_t rp0_pid:2; 312 uint64_t reserved_15_15:1; 313 uint64_t prt_sel:3; 314 uint64_t lttr:4; 315 uint64_t prio:4; 316 uint64_t mbox:4; 317#else 318 uint64_t mbox:4; 319 uint64_t prio:4; 320 uint64_t lttr:4; 321 uint64_t prt_sel:3; 322 uint64_t reserved_15_15:1; 323 uint64_t rp0_pid:2; 324 uint64_t rp1_pid:1; 325 uint64_t rp0_sid:2; 326 uint64_t rp1_sid:1; 327 uint64_t reserved_22_23:2; 328 uint64_t rsp_thr:6; 329 uint64_t reserved_30_30:1; 330 uint64_t to_mode:1; 331 uint64_t reserved_32_63:32; 332#endif 333 } s; 334}; 335 336union cvmx_sriox_imsg_inst_hdrx { 337 uint64_t u64; 338 struct cvmx_sriox_imsg_inst_hdrx_s { 339#ifdef __BIG_ENDIAN_BITFIELD 340 uint64_t r:1; 341 uint64_t reserved_58_62:5; 342 uint64_t pm:2; 343 uint64_t reserved_55_55:1; 344 uint64_t sl:7; 345 uint64_t reserved_46_47:2; 346 uint64_t nqos:1; 347 uint64_t ngrp:1; 348 uint64_t ntt:1; 349 uint64_t ntag:1; 350 uint64_t reserved_35_41:7; 351 uint64_t rs:1; 352 uint64_t tt:2; 353 uint64_t tag:32; 354#else 355 uint64_t tag:32; 356 uint64_t tt:2; 357 uint64_t rs:1; 358 uint64_t reserved_35_41:7; 359 uint64_t ntag:1; 360 uint64_t ntt:1; 361 uint64_t ngrp:1; 362 uint64_t nqos:1; 363 uint64_t reserved_46_47:2; 364 uint64_t sl:7; 365 uint64_t reserved_55_55:1; 366 uint64_t pm:2; 367 uint64_t reserved_58_62:5; 368 uint64_t r:1; 369#endif 370 } s; 371}; 372 373union cvmx_sriox_imsg_qos_grpx { 374 uint64_t u64; 375 struct cvmx_sriox_imsg_qos_grpx_s { 376#ifdef __BIG_ENDIAN_BITFIELD 377 uint64_t reserved_63_63:1; 378 uint64_t qos7:3; 379 uint64_t grp7:4; 380 uint64_t reserved_55_55:1; 381 uint64_t qos6:3; 382 uint64_t grp6:4; 383 uint64_t reserved_47_47:1; 384 uint64_t qos5:3; 385 uint64_t grp5:4; 386 uint64_t reserved_39_39:1; 387 uint64_t qos4:3; 388 uint64_t grp4:4; 389 uint64_t reserved_31_31:1; 390 uint64_t qos3:3; 391 uint64_t grp3:4; 392 uint64_t reserved_23_23:1; 393 uint64_t qos2:3; 394 uint64_t grp2:4; 395 uint64_t reserved_15_15:1; 396 uint64_t qos1:3; 397 uint64_t grp1:4; 398 uint64_t reserved_7_7:1; 399 uint64_t qos0:3; 400 uint64_t grp0:4; 401#else 402 uint64_t grp0:4; 403 uint64_t qos0:3; 404 uint64_t reserved_7_7:1; 405 uint64_t grp1:4; 406 uint64_t qos1:3; 407 uint64_t reserved_15_15:1; 408 uint64_t grp2:4; 409 uint64_t qos2:3; 410 uint64_t reserved_23_23:1; 411 uint64_t grp3:4; 412 uint64_t qos3:3; 413 uint64_t reserved_31_31:1; 414 uint64_t grp4:4; 415 uint64_t qos4:3; 416 uint64_t reserved_39_39:1; 417 uint64_t grp5:4; 418 uint64_t qos5:3; 419 uint64_t reserved_47_47:1; 420 uint64_t grp6:4; 421 uint64_t qos6:3; 422 uint64_t reserved_55_55:1; 423 uint64_t grp7:4; 424 uint64_t qos7:3; 425 uint64_t reserved_63_63:1; 426#endif 427 } s; 428}; 429 430union cvmx_sriox_imsg_statusx { 431 uint64_t u64; 432 struct cvmx_sriox_imsg_statusx_s { 433#ifdef __BIG_ENDIAN_BITFIELD 434 uint64_t val1:1; 435 uint64_t err1:1; 436 uint64_t toe1:1; 437 uint64_t toc1:1; 438 uint64_t prt1:1; 439 uint64_t reserved_58_58:1; 440 uint64_t tt1:1; 441 uint64_t dis1:1; 442 uint64_t seg1:4; 443 uint64_t mbox1:2; 444 uint64_t lttr1:2; 445 uint64_t sid1:16; 446 uint64_t val0:1; 447 uint64_t err0:1; 448 uint64_t toe0:1; 449 uint64_t toc0:1; 450 uint64_t prt0:1; 451 uint64_t reserved_26_26:1; 452 uint64_t tt0:1; 453 uint64_t dis0:1; 454 uint64_t seg0:4; 455 uint64_t mbox0:2; 456 uint64_t lttr0:2; 457 uint64_t sid0:16; 458#else 459 uint64_t sid0:16; 460 uint64_t lttr0:2; 461 uint64_t mbox0:2; 462 uint64_t seg0:4; 463 uint64_t dis0:1; 464 uint64_t tt0:1; 465 uint64_t reserved_26_26:1; 466 uint64_t prt0:1; 467 uint64_t toc0:1; 468 uint64_t toe0:1; 469 uint64_t err0:1; 470 uint64_t val0:1; 471 uint64_t sid1:16; 472 uint64_t lttr1:2; 473 uint64_t mbox1:2; 474 uint64_t seg1:4; 475 uint64_t dis1:1; 476 uint64_t tt1:1; 477 uint64_t reserved_58_58:1; 478 uint64_t prt1:1; 479 uint64_t toc1:1; 480 uint64_t toe1:1; 481 uint64_t err1:1; 482 uint64_t val1:1; 483#endif 484 } s; 485}; 486 487union cvmx_sriox_imsg_vport_thr { 488 uint64_t u64; 489 struct cvmx_sriox_imsg_vport_thr_s { 490#ifdef __BIG_ENDIAN_BITFIELD 491 uint64_t reserved_54_63:10; 492 uint64_t max_tot:6; 493 uint64_t reserved_46_47:2; 494 uint64_t max_s1:6; 495 uint64_t reserved_38_39:2; 496 uint64_t max_s0:6; 497 uint64_t sp_vport:1; 498 uint64_t reserved_20_30:11; 499 uint64_t buf_thr:4; 500 uint64_t reserved_14_15:2; 501 uint64_t max_p1:6; 502 uint64_t reserved_6_7:2; 503 uint64_t max_p0:6; 504#else 505 uint64_t max_p0:6; 506 uint64_t reserved_6_7:2; 507 uint64_t max_p1:6; 508 uint64_t reserved_14_15:2; 509 uint64_t buf_thr:4; 510 uint64_t reserved_20_30:11; 511 uint64_t sp_vport:1; 512 uint64_t max_s0:6; 513 uint64_t reserved_38_39:2; 514 uint64_t max_s1:6; 515 uint64_t reserved_46_47:2; 516 uint64_t max_tot:6; 517 uint64_t reserved_54_63:10; 518#endif 519 } s; 520}; 521 522union cvmx_sriox_imsg_vport_thr2 { 523 uint64_t u64; 524 struct cvmx_sriox_imsg_vport_thr2_s { 525#ifdef __BIG_ENDIAN_BITFIELD 526 uint64_t reserved_46_63:18; 527 uint64_t max_s3:6; 528 uint64_t reserved_38_39:2; 529 uint64_t max_s2:6; 530 uint64_t reserved_0_31:32; 531#else 532 uint64_t reserved_0_31:32; 533 uint64_t max_s2:6; 534 uint64_t reserved_38_39:2; 535 uint64_t max_s3:6; 536 uint64_t reserved_46_63:18; 537#endif 538 } s; 539}; 540 541union cvmx_sriox_int2_enable { 542 uint64_t u64; 543 struct cvmx_sriox_int2_enable_s { 544#ifdef __BIG_ENDIAN_BITFIELD 545 uint64_t reserved_1_63:63; 546 uint64_t pko_rst:1; 547#else 548 uint64_t pko_rst:1; 549 uint64_t reserved_1_63:63; 550#endif 551 } s; 552}; 553 554union cvmx_sriox_int2_reg { 555 uint64_t u64; 556 struct cvmx_sriox_int2_reg_s { 557#ifdef __BIG_ENDIAN_BITFIELD 558 uint64_t reserved_32_63:32; 559 uint64_t int_sum:1; 560 uint64_t reserved_1_30:30; 561 uint64_t pko_rst:1; 562#else 563 uint64_t pko_rst:1; 564 uint64_t reserved_1_30:30; 565 uint64_t int_sum:1; 566 uint64_t reserved_32_63:32; 567#endif 568 } s; 569}; 570 571union cvmx_sriox_int_enable { 572 uint64_t u64; 573 struct cvmx_sriox_int_enable_s { 574#ifdef __BIG_ENDIAN_BITFIELD 575 uint64_t reserved_27_63:37; 576 uint64_t zero_pkt:1; 577 uint64_t ttl_tout:1; 578 uint64_t fail:1; 579 uint64_t degrade:1; 580 uint64_t mac_buf:1; 581 uint64_t f_error:1; 582 uint64_t rtry_err:1; 583 uint64_t pko_err:1; 584 uint64_t omsg_err:1; 585 uint64_t omsg1:1; 586 uint64_t omsg0:1; 587 uint64_t link_up:1; 588 uint64_t link_dwn:1; 589 uint64_t phy_erb:1; 590 uint64_t log_erb:1; 591 uint64_t soft_rx:1; 592 uint64_t soft_tx:1; 593 uint64_t mce_rx:1; 594 uint64_t mce_tx:1; 595 uint64_t wr_done:1; 596 uint64_t sli_err:1; 597 uint64_t deny_wr:1; 598 uint64_t bar_err:1; 599 uint64_t maint_op:1; 600 uint64_t rxbell:1; 601 uint64_t bell_err:1; 602 uint64_t txbell:1; 603#else 604 uint64_t txbell:1; 605 uint64_t bell_err:1; 606 uint64_t rxbell:1; 607 uint64_t maint_op:1; 608 uint64_t bar_err:1; 609 uint64_t deny_wr:1; 610 uint64_t sli_err:1; 611 uint64_t wr_done:1; 612 uint64_t mce_tx:1; 613 uint64_t mce_rx:1; 614 uint64_t soft_tx:1; 615 uint64_t soft_rx:1; 616 uint64_t log_erb:1; 617 uint64_t phy_erb:1; 618 uint64_t link_dwn:1; 619 uint64_t link_up:1; 620 uint64_t omsg0:1; 621 uint64_t omsg1:1; 622 uint64_t omsg_err:1; 623 uint64_t pko_err:1; 624 uint64_t rtry_err:1; 625 uint64_t f_error:1; 626 uint64_t mac_buf:1; 627 uint64_t degrade:1; 628 uint64_t fail:1; 629 uint64_t ttl_tout:1; 630 uint64_t zero_pkt:1; 631 uint64_t reserved_27_63:37; 632#endif 633 } s; 634 struct cvmx_sriox_int_enable_cn63xxp1 { 635#ifdef __BIG_ENDIAN_BITFIELD 636 uint64_t reserved_22_63:42; 637 uint64_t f_error:1; 638 uint64_t rtry_err:1; 639 uint64_t pko_err:1; 640 uint64_t omsg_err:1; 641 uint64_t omsg1:1; 642 uint64_t omsg0:1; 643 uint64_t link_up:1; 644 uint64_t link_dwn:1; 645 uint64_t phy_erb:1; 646 uint64_t log_erb:1; 647 uint64_t soft_rx:1; 648 uint64_t soft_tx:1; 649 uint64_t mce_rx:1; 650 uint64_t mce_tx:1; 651 uint64_t wr_done:1; 652 uint64_t sli_err:1; 653 uint64_t deny_wr:1; 654 uint64_t bar_err:1; 655 uint64_t maint_op:1; 656 uint64_t rxbell:1; 657 uint64_t bell_err:1; 658 uint64_t txbell:1; 659#else 660 uint64_t txbell:1; 661 uint64_t bell_err:1; 662 uint64_t rxbell:1; 663 uint64_t maint_op:1; 664 uint64_t bar_err:1; 665 uint64_t deny_wr:1; 666 uint64_t sli_err:1; 667 uint64_t wr_done:1; 668 uint64_t mce_tx:1; 669 uint64_t mce_rx:1; 670 uint64_t soft_tx:1; 671 uint64_t soft_rx:1; 672 uint64_t log_erb:1; 673 uint64_t phy_erb:1; 674 uint64_t link_dwn:1; 675 uint64_t link_up:1; 676 uint64_t omsg0:1; 677 uint64_t omsg1:1; 678 uint64_t omsg_err:1; 679 uint64_t pko_err:1; 680 uint64_t rtry_err:1; 681 uint64_t f_error:1; 682 uint64_t reserved_22_63:42; 683#endif 684 } cn63xxp1; 685}; 686 687union cvmx_sriox_int_info0 { 688 uint64_t u64; 689 struct cvmx_sriox_int_info0_s { 690#ifdef __BIG_ENDIAN_BITFIELD 691 uint64_t cmd:4; 692 uint64_t type:4; 693 uint64_t tag:8; 694 uint64_t reserved_42_47:6; 695 uint64_t length:10; 696 uint64_t status:3; 697 uint64_t reserved_16_28:13; 698 uint64_t be0:8; 699 uint64_t be1:8; 700#else 701 uint64_t be1:8; 702 uint64_t be0:8; 703 uint64_t reserved_16_28:13; 704 uint64_t status:3; 705 uint64_t length:10; 706 uint64_t reserved_42_47:6; 707 uint64_t tag:8; 708 uint64_t type:4; 709 uint64_t cmd:4; 710#endif 711 } s; 712}; 713 714union cvmx_sriox_int_info1 { 715 uint64_t u64; 716 struct cvmx_sriox_int_info1_s { 717#ifdef __BIG_ENDIAN_BITFIELD 718 uint64_t info1:64; 719#else 720 uint64_t info1:64; 721#endif 722 } s; 723}; 724 725union cvmx_sriox_int_info2 { 726 uint64_t u64; 727 struct cvmx_sriox_int_info2_s { 728#ifdef __BIG_ENDIAN_BITFIELD 729 uint64_t prio:2; 730 uint64_t tt:1; 731 uint64_t sis:1; 732 uint64_t ssize:4; 733 uint64_t did:16; 734 uint64_t xmbox:4; 735 uint64_t mbox:2; 736 uint64_t letter:2; 737 uint64_t rsrvd:30; 738 uint64_t lns:1; 739 uint64_t intr:1; 740#else 741 uint64_t intr:1; 742 uint64_t lns:1; 743 uint64_t rsrvd:30; 744 uint64_t letter:2; 745 uint64_t mbox:2; 746 uint64_t xmbox:4; 747 uint64_t did:16; 748 uint64_t ssize:4; 749 uint64_t sis:1; 750 uint64_t tt:1; 751 uint64_t prio:2; 752#endif 753 } s; 754}; 755 756union cvmx_sriox_int_info3 { 757 uint64_t u64; 758 struct cvmx_sriox_int_info3_s { 759#ifdef __BIG_ENDIAN_BITFIELD 760 uint64_t prio:2; 761 uint64_t tt:2; 762 uint64_t type:4; 763 uint64_t other:48; 764 uint64_t reserved_0_7:8; 765#else 766 uint64_t reserved_0_7:8; 767 uint64_t other:48; 768 uint64_t type:4; 769 uint64_t tt:2; 770 uint64_t prio:2; 771#endif 772 } s; 773}; 774 775union cvmx_sriox_int_reg { 776 uint64_t u64; 777 struct cvmx_sriox_int_reg_s { 778#ifdef __BIG_ENDIAN_BITFIELD 779 uint64_t reserved_32_63:32; 780 uint64_t int2_sum:1; 781 uint64_t reserved_27_30:4; 782 uint64_t zero_pkt:1; 783 uint64_t ttl_tout:1; 784 uint64_t fail:1; 785 uint64_t degrad:1; 786 uint64_t mac_buf:1; 787 uint64_t f_error:1; 788 uint64_t rtry_err:1; 789 uint64_t pko_err:1; 790 uint64_t omsg_err:1; 791 uint64_t omsg1:1; 792 uint64_t omsg0:1; 793 uint64_t link_up:1; 794 uint64_t link_dwn:1; 795 uint64_t phy_erb:1; 796 uint64_t log_erb:1; 797 uint64_t soft_rx:1; 798 uint64_t soft_tx:1; 799 uint64_t mce_rx:1; 800 uint64_t mce_tx:1; 801 uint64_t wr_done:1; 802 uint64_t sli_err:1; 803 uint64_t deny_wr:1; 804 uint64_t bar_err:1; 805 uint64_t maint_op:1; 806 uint64_t rxbell:1; 807 uint64_t bell_err:1; 808 uint64_t txbell:1; 809#else 810 uint64_t txbell:1; 811 uint64_t bell_err:1; 812 uint64_t rxbell:1; 813 uint64_t maint_op:1; 814 uint64_t bar_err:1; 815 uint64_t deny_wr:1; 816 uint64_t sli_err:1; 817 uint64_t wr_done:1; 818 uint64_t mce_tx:1; 819 uint64_t mce_rx:1; 820 uint64_t soft_tx:1; 821 uint64_t soft_rx:1; 822 uint64_t log_erb:1; 823 uint64_t phy_erb:1; 824 uint64_t link_dwn:1; 825 uint64_t link_up:1; 826 uint64_t omsg0:1; 827 uint64_t omsg1:1; 828 uint64_t omsg_err:1; 829 uint64_t pko_err:1; 830 uint64_t rtry_err:1; 831 uint64_t f_error:1; 832 uint64_t mac_buf:1; 833 uint64_t degrad:1; 834 uint64_t fail:1; 835 uint64_t ttl_tout:1; 836 uint64_t zero_pkt:1; 837 uint64_t reserved_27_30:4; 838 uint64_t int2_sum:1; 839 uint64_t reserved_32_63:32; 840#endif 841 } s; 842 struct cvmx_sriox_int_reg_cn63xxp1 { 843#ifdef __BIG_ENDIAN_BITFIELD 844 uint64_t reserved_22_63:42; 845 uint64_t f_error:1; 846 uint64_t rtry_err:1; 847 uint64_t pko_err:1; 848 uint64_t omsg_err:1; 849 uint64_t omsg1:1; 850 uint64_t omsg0:1; 851 uint64_t link_up:1; 852 uint64_t link_dwn:1; 853 uint64_t phy_erb:1; 854 uint64_t log_erb:1; 855 uint64_t soft_rx:1; 856 uint64_t soft_tx:1; 857 uint64_t mce_rx:1; 858 uint64_t mce_tx:1; 859 uint64_t wr_done:1; 860 uint64_t sli_err:1; 861 uint64_t deny_wr:1; 862 uint64_t bar_err:1; 863 uint64_t maint_op:1; 864 uint64_t rxbell:1; 865 uint64_t bell_err:1; 866 uint64_t txbell:1; 867#else 868 uint64_t txbell:1; 869 uint64_t bell_err:1; 870 uint64_t rxbell:1; 871 uint64_t maint_op:1; 872 uint64_t bar_err:1; 873 uint64_t deny_wr:1; 874 uint64_t sli_err:1; 875 uint64_t wr_done:1; 876 uint64_t mce_tx:1; 877 uint64_t mce_rx:1; 878 uint64_t soft_tx:1; 879 uint64_t soft_rx:1; 880 uint64_t log_erb:1; 881 uint64_t phy_erb:1; 882 uint64_t link_dwn:1; 883 uint64_t link_up:1; 884 uint64_t omsg0:1; 885 uint64_t omsg1:1; 886 uint64_t omsg_err:1; 887 uint64_t pko_err:1; 888 uint64_t rtry_err:1; 889 uint64_t f_error:1; 890 uint64_t reserved_22_63:42; 891#endif 892 } cn63xxp1; 893}; 894 895union cvmx_sriox_ip_feature { 896 uint64_t u64; 897 struct cvmx_sriox_ip_feature_s { 898#ifdef __BIG_ENDIAN_BITFIELD 899 uint64_t ops:32; 900 uint64_t reserved_15_31:17; 901 uint64_t no_vmin:1; 902 uint64_t a66:1; 903 uint64_t a50:1; 904 uint64_t reserved_11_11:1; 905 uint64_t tx_flow:1; 906 uint64_t pt_width:2; 907 uint64_t tx_pol:4; 908 uint64_t rx_pol:4; 909#else 910 uint64_t rx_pol:4; 911 uint64_t tx_pol:4; 912 uint64_t pt_width:2; 913 uint64_t tx_flow:1; 914 uint64_t reserved_11_11:1; 915 uint64_t a50:1; 916 uint64_t a66:1; 917 uint64_t no_vmin:1; 918 uint64_t reserved_15_31:17; 919 uint64_t ops:32; 920#endif 921 } s; 922 struct cvmx_sriox_ip_feature_cn63xx { 923#ifdef __BIG_ENDIAN_BITFIELD 924 uint64_t ops:32; 925 uint64_t reserved_14_31:18; 926 uint64_t a66:1; 927 uint64_t a50:1; 928 uint64_t reserved_11_11:1; 929 uint64_t tx_flow:1; 930 uint64_t pt_width:2; 931 uint64_t tx_pol:4; 932 uint64_t rx_pol:4; 933#else 934 uint64_t rx_pol:4; 935 uint64_t tx_pol:4; 936 uint64_t pt_width:2; 937 uint64_t tx_flow:1; 938 uint64_t reserved_11_11:1; 939 uint64_t a50:1; 940 uint64_t a66:1; 941 uint64_t reserved_14_31:18; 942 uint64_t ops:32; 943#endif 944 } cn63xx; 945}; 946 947union cvmx_sriox_mac_buffers { 948 uint64_t u64; 949 struct cvmx_sriox_mac_buffers_s { 950#ifdef __BIG_ENDIAN_BITFIELD 951 uint64_t reserved_56_63:8; 952 uint64_t tx_enb:8; 953 uint64_t reserved_44_47:4; 954 uint64_t tx_inuse:4; 955 uint64_t tx_stat:8; 956 uint64_t reserved_24_31:8; 957 uint64_t rx_enb:8; 958 uint64_t reserved_12_15:4; 959 uint64_t rx_inuse:4; 960 uint64_t rx_stat:8; 961#else 962 uint64_t rx_stat:8; 963 uint64_t rx_inuse:4; 964 uint64_t reserved_12_15:4; 965 uint64_t rx_enb:8; 966 uint64_t reserved_24_31:8; 967 uint64_t tx_stat:8; 968 uint64_t tx_inuse:4; 969 uint64_t reserved_44_47:4; 970 uint64_t tx_enb:8; 971 uint64_t reserved_56_63:8; 972#endif 973 } s; 974}; 975 976union cvmx_sriox_maint_op { 977 uint64_t u64; 978 struct cvmx_sriox_maint_op_s { 979#ifdef __BIG_ENDIAN_BITFIELD 980 uint64_t wr_data:32; 981 uint64_t reserved_27_31:5; 982 uint64_t fail:1; 983 uint64_t pending:1; 984 uint64_t op:1; 985 uint64_t addr:24; 986#else 987 uint64_t addr:24; 988 uint64_t op:1; 989 uint64_t pending:1; 990 uint64_t fail:1; 991 uint64_t reserved_27_31:5; 992 uint64_t wr_data:32; 993#endif 994 } s; 995}; 996 997union cvmx_sriox_maint_rd_data { 998 uint64_t u64; 999 struct cvmx_sriox_maint_rd_data_s { 1000#ifdef __BIG_ENDIAN_BITFIELD 1001 uint64_t reserved_33_63:31; 1002 uint64_t valid:1; 1003 uint64_t rd_data:32; 1004#else 1005 uint64_t rd_data:32; 1006 uint64_t valid:1; 1007 uint64_t reserved_33_63:31; 1008#endif 1009 } s; 1010}; 1011 1012union cvmx_sriox_mce_tx_ctl { 1013 uint64_t u64; 1014 struct cvmx_sriox_mce_tx_ctl_s { 1015#ifdef __BIG_ENDIAN_BITFIELD 1016 uint64_t reserved_1_63:63; 1017 uint64_t mce:1; 1018#else 1019 uint64_t mce:1; 1020 uint64_t reserved_1_63:63; 1021#endif 1022 } s; 1023}; 1024 1025union cvmx_sriox_mem_op_ctrl { 1026 uint64_t u64; 1027 struct cvmx_sriox_mem_op_ctrl_s { 1028#ifdef __BIG_ENDIAN_BITFIELD 1029 uint64_t reserved_10_63:54; 1030 uint64_t rr_ro:1; 1031 uint64_t w_ro:1; 1032 uint64_t reserved_6_7:2; 1033 uint64_t rp1_sid:1; 1034 uint64_t rp0_sid:2; 1035 uint64_t rp1_pid:1; 1036 uint64_t rp0_pid:2; 1037#else 1038 uint64_t rp0_pid:2; 1039 uint64_t rp1_pid:1; 1040 uint64_t rp0_sid:2; 1041 uint64_t rp1_sid:1; 1042 uint64_t reserved_6_7:2; 1043 uint64_t w_ro:1; 1044 uint64_t rr_ro:1; 1045 uint64_t reserved_10_63:54; 1046#endif 1047 } s; 1048}; 1049 1050union cvmx_sriox_omsg_ctrlx { 1051 uint64_t u64; 1052 struct cvmx_sriox_omsg_ctrlx_s { 1053#ifdef __BIG_ENDIAN_BITFIELD 1054 uint64_t testmode:1; 1055 uint64_t reserved_37_62:26; 1056 uint64_t silo_max:5; 1057 uint64_t rtry_thr:16; 1058 uint64_t rtry_en:1; 1059 uint64_t reserved_11_14:4; 1060 uint64_t idm_tt:1; 1061 uint64_t idm_sis:1; 1062 uint64_t idm_did:1; 1063 uint64_t lttr_sp:4; 1064 uint64_t lttr_mp:4; 1065#else 1066 uint64_t lttr_mp:4; 1067 uint64_t lttr_sp:4; 1068 uint64_t idm_did:1; 1069 uint64_t idm_sis:1; 1070 uint64_t idm_tt:1; 1071 uint64_t reserved_11_14:4; 1072 uint64_t rtry_en:1; 1073 uint64_t rtry_thr:16; 1074 uint64_t silo_max:5; 1075 uint64_t reserved_37_62:26; 1076 uint64_t testmode:1; 1077#endif 1078 } s; 1079 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { 1080#ifdef __BIG_ENDIAN_BITFIELD 1081 uint64_t testmode:1; 1082 uint64_t reserved_32_62:31; 1083 uint64_t rtry_thr:16; 1084 uint64_t rtry_en:1; 1085 uint64_t reserved_11_14:4; 1086 uint64_t idm_tt:1; 1087 uint64_t idm_sis:1; 1088 uint64_t idm_did:1; 1089 uint64_t lttr_sp:4; 1090 uint64_t lttr_mp:4; 1091#else 1092 uint64_t lttr_mp:4; 1093 uint64_t lttr_sp:4; 1094 uint64_t idm_did:1; 1095 uint64_t idm_sis:1; 1096 uint64_t idm_tt:1; 1097 uint64_t reserved_11_14:4; 1098 uint64_t rtry_en:1; 1099 uint64_t rtry_thr:16; 1100 uint64_t reserved_32_62:31; 1101 uint64_t testmode:1; 1102#endif 1103 } cn63xxp1; 1104}; 1105 1106union cvmx_sriox_omsg_done_countsx { 1107 uint64_t u64; 1108 struct cvmx_sriox_omsg_done_countsx_s { 1109#ifdef __BIG_ENDIAN_BITFIELD 1110 uint64_t reserved_32_63:32; 1111 uint64_t bad:16; 1112 uint64_t good:16; 1113#else 1114 uint64_t good:16; 1115 uint64_t bad:16; 1116 uint64_t reserved_32_63:32; 1117#endif 1118 } s; 1119}; 1120 1121union cvmx_sriox_omsg_fmp_mrx { 1122 uint64_t u64; 1123 struct cvmx_sriox_omsg_fmp_mrx_s { 1124#ifdef __BIG_ENDIAN_BITFIELD 1125 uint64_t reserved_15_63:49; 1126 uint64_t ctlr_sp:1; 1127 uint64_t ctlr_fmp:1; 1128 uint64_t ctlr_nmp:1; 1129 uint64_t id_sp:1; 1130 uint64_t id_fmp:1; 1131 uint64_t id_nmp:1; 1132 uint64_t id_psd:1; 1133 uint64_t mbox_sp:1; 1134 uint64_t mbox_fmp:1; 1135 uint64_t mbox_nmp:1; 1136 uint64_t mbox_psd:1; 1137 uint64_t all_sp:1; 1138 uint64_t all_fmp:1; 1139 uint64_t all_nmp:1; 1140 uint64_t all_psd:1; 1141#else 1142 uint64_t all_psd:1; 1143 uint64_t all_nmp:1; 1144 uint64_t all_fmp:1; 1145 uint64_t all_sp:1; 1146 uint64_t mbox_psd:1; 1147 uint64_t mbox_nmp:1; 1148 uint64_t mbox_fmp:1; 1149 uint64_t mbox_sp:1; 1150 uint64_t id_psd:1; 1151 uint64_t id_nmp:1; 1152 uint64_t id_fmp:1; 1153 uint64_t id_sp:1; 1154 uint64_t ctlr_nmp:1; 1155 uint64_t ctlr_fmp:1; 1156 uint64_t ctlr_sp:1; 1157 uint64_t reserved_15_63:49; 1158#endif 1159 } s; 1160}; 1161 1162union cvmx_sriox_omsg_nmp_mrx { 1163 uint64_t u64; 1164 struct cvmx_sriox_omsg_nmp_mrx_s { 1165#ifdef __BIG_ENDIAN_BITFIELD 1166 uint64_t reserved_15_63:49; 1167 uint64_t ctlr_sp:1; 1168 uint64_t ctlr_fmp:1; 1169 uint64_t ctlr_nmp:1; 1170 uint64_t id_sp:1; 1171 uint64_t id_fmp:1; 1172 uint64_t id_nmp:1; 1173 uint64_t reserved_8_8:1; 1174 uint64_t mbox_sp:1; 1175 uint64_t mbox_fmp:1; 1176 uint64_t mbox_nmp:1; 1177 uint64_t reserved_4_4:1; 1178 uint64_t all_sp:1; 1179 uint64_t all_fmp:1; 1180 uint64_t all_nmp:1; 1181 uint64_t reserved_0_0:1; 1182#else 1183 uint64_t reserved_0_0:1; 1184 uint64_t all_nmp:1; 1185 uint64_t all_fmp:1; 1186 uint64_t all_sp:1; 1187 uint64_t reserved_4_4:1; 1188 uint64_t mbox_nmp:1; 1189 uint64_t mbox_fmp:1; 1190 uint64_t mbox_sp:1; 1191 uint64_t reserved_8_8:1; 1192 uint64_t id_nmp:1; 1193 uint64_t id_fmp:1; 1194 uint64_t id_sp:1; 1195 uint64_t ctlr_nmp:1; 1196 uint64_t ctlr_fmp:1; 1197 uint64_t ctlr_sp:1; 1198 uint64_t reserved_15_63:49; 1199#endif 1200 } s; 1201}; 1202 1203union cvmx_sriox_omsg_portx { 1204 uint64_t u64; 1205 struct cvmx_sriox_omsg_portx_s { 1206#ifdef __BIG_ENDIAN_BITFIELD 1207 uint64_t reserved_32_63:32; 1208 uint64_t enable:1; 1209 uint64_t reserved_3_30:28; 1210 uint64_t port:3; 1211#else 1212 uint64_t port:3; 1213 uint64_t reserved_3_30:28; 1214 uint64_t enable:1; 1215 uint64_t reserved_32_63:32; 1216#endif 1217 } s; 1218 struct cvmx_sriox_omsg_portx_cn63xx { 1219#ifdef __BIG_ENDIAN_BITFIELD 1220 uint64_t reserved_32_63:32; 1221 uint64_t enable:1; 1222 uint64_t reserved_2_30:29; 1223 uint64_t port:2; 1224#else 1225 uint64_t port:2; 1226 uint64_t reserved_2_30:29; 1227 uint64_t enable:1; 1228 uint64_t reserved_32_63:32; 1229#endif 1230 } cn63xx; 1231}; 1232 1233union cvmx_sriox_omsg_silo_thr { 1234 uint64_t u64; 1235 struct cvmx_sriox_omsg_silo_thr_s { 1236#ifdef __BIG_ENDIAN_BITFIELD 1237 uint64_t reserved_5_63:59; 1238 uint64_t tot_silo:5; 1239#else 1240 uint64_t tot_silo:5; 1241 uint64_t reserved_5_63:59; 1242#endif 1243 } s; 1244}; 1245 1246union cvmx_sriox_omsg_sp_mrx { 1247 uint64_t u64; 1248 struct cvmx_sriox_omsg_sp_mrx_s { 1249#ifdef __BIG_ENDIAN_BITFIELD 1250 uint64_t reserved_16_63:48; 1251 uint64_t xmbox_sp:1; 1252 uint64_t ctlr_sp:1; 1253 uint64_t ctlr_fmp:1; 1254 uint64_t ctlr_nmp:1; 1255 uint64_t id_sp:1; 1256 uint64_t id_fmp:1; 1257 uint64_t id_nmp:1; 1258 uint64_t id_psd:1; 1259 uint64_t mbox_sp:1; 1260 uint64_t mbox_fmp:1; 1261 uint64_t mbox_nmp:1; 1262 uint64_t mbox_psd:1; 1263 uint64_t all_sp:1; 1264 uint64_t all_fmp:1; 1265 uint64_t all_nmp:1; 1266 uint64_t all_psd:1; 1267#else 1268 uint64_t all_psd:1; 1269 uint64_t all_nmp:1; 1270 uint64_t all_fmp:1; 1271 uint64_t all_sp:1; 1272 uint64_t mbox_psd:1; 1273 uint64_t mbox_nmp:1; 1274 uint64_t mbox_fmp:1; 1275 uint64_t mbox_sp:1; 1276 uint64_t id_psd:1; 1277 uint64_t id_nmp:1; 1278 uint64_t id_fmp:1; 1279 uint64_t id_sp:1; 1280 uint64_t ctlr_nmp:1; 1281 uint64_t ctlr_fmp:1; 1282 uint64_t ctlr_sp:1; 1283 uint64_t xmbox_sp:1; 1284 uint64_t reserved_16_63:48; 1285#endif 1286 } s; 1287}; 1288 1289union cvmx_sriox_priox_in_use { 1290 uint64_t u64; 1291 struct cvmx_sriox_priox_in_use_s { 1292#ifdef __BIG_ENDIAN_BITFIELD 1293 uint64_t reserved_32_63:32; 1294 uint64_t end_cnt:16; 1295 uint64_t start_cnt:16; 1296#else 1297 uint64_t start_cnt:16; 1298 uint64_t end_cnt:16; 1299 uint64_t reserved_32_63:32; 1300#endif 1301 } s; 1302}; 1303 1304union cvmx_sriox_rx_bell { 1305 uint64_t u64; 1306 struct cvmx_sriox_rx_bell_s { 1307#ifdef __BIG_ENDIAN_BITFIELD 1308 uint64_t reserved_48_63:16; 1309 uint64_t data:16; 1310 uint64_t src_id:16; 1311 uint64_t count:8; 1312 uint64_t reserved_5_7:3; 1313 uint64_t dest_id:1; 1314 uint64_t id16:1; 1315 uint64_t reserved_2_2:1; 1316 uint64_t priority:2; 1317#else 1318 uint64_t priority:2; 1319 uint64_t reserved_2_2:1; 1320 uint64_t id16:1; 1321 uint64_t dest_id:1; 1322 uint64_t reserved_5_7:3; 1323 uint64_t count:8; 1324 uint64_t src_id:16; 1325 uint64_t data:16; 1326 uint64_t reserved_48_63:16; 1327#endif 1328 } s; 1329}; 1330 1331union cvmx_sriox_rx_bell_seq { 1332 uint64_t u64; 1333 struct cvmx_sriox_rx_bell_seq_s { 1334#ifdef __BIG_ENDIAN_BITFIELD 1335 uint64_t reserved_40_63:24; 1336 uint64_t count:8; 1337 uint64_t seq:32; 1338#else 1339 uint64_t seq:32; 1340 uint64_t count:8; 1341 uint64_t reserved_40_63:24; 1342#endif 1343 } s; 1344}; 1345 1346union cvmx_sriox_rx_status { 1347 uint64_t u64; 1348 struct cvmx_sriox_rx_status_s { 1349#ifdef __BIG_ENDIAN_BITFIELD 1350 uint64_t rtn_pr3:8; 1351 uint64_t rtn_pr2:8; 1352 uint64_t rtn_pr1:8; 1353 uint64_t reserved_28_39:12; 1354 uint64_t mbox:4; 1355 uint64_t comp:8; 1356 uint64_t reserved_13_15:3; 1357 uint64_t n_post:5; 1358 uint64_t post:8; 1359#else 1360 uint64_t post:8; 1361 uint64_t n_post:5; 1362 uint64_t reserved_13_15:3; 1363 uint64_t comp:8; 1364 uint64_t mbox:4; 1365 uint64_t reserved_28_39:12; 1366 uint64_t rtn_pr1:8; 1367 uint64_t rtn_pr2:8; 1368 uint64_t rtn_pr3:8; 1369#endif 1370 } s; 1371}; 1372 1373union cvmx_sriox_s2m_typex { 1374 uint64_t u64; 1375 struct cvmx_sriox_s2m_typex_s { 1376#ifdef __BIG_ENDIAN_BITFIELD 1377 uint64_t reserved_19_63:45; 1378 uint64_t wr_op:3; 1379 uint64_t reserved_15_15:1; 1380 uint64_t rd_op:3; 1381 uint64_t wr_prior:2; 1382 uint64_t rd_prior:2; 1383 uint64_t reserved_6_7:2; 1384 uint64_t src_id:1; 1385 uint64_t id16:1; 1386 uint64_t reserved_2_3:2; 1387 uint64_t iaow_sel:2; 1388#else 1389 uint64_t iaow_sel:2; 1390 uint64_t reserved_2_3:2; 1391 uint64_t id16:1; 1392 uint64_t src_id:1; 1393 uint64_t reserved_6_7:2; 1394 uint64_t rd_prior:2; 1395 uint64_t wr_prior:2; 1396 uint64_t rd_op:3; 1397 uint64_t reserved_15_15:1; 1398 uint64_t wr_op:3; 1399 uint64_t reserved_19_63:45; 1400#endif 1401 } s; 1402}; 1403 1404union cvmx_sriox_seq { 1405 uint64_t u64; 1406 struct cvmx_sriox_seq_s { 1407#ifdef __BIG_ENDIAN_BITFIELD 1408 uint64_t reserved_32_63:32; 1409 uint64_t seq:32; 1410#else 1411 uint64_t seq:32; 1412 uint64_t reserved_32_63:32; 1413#endif 1414 } s; 1415}; 1416 1417union cvmx_sriox_status_reg { 1418 uint64_t u64; 1419 struct cvmx_sriox_status_reg_s { 1420#ifdef __BIG_ENDIAN_BITFIELD 1421 uint64_t reserved_2_63:62; 1422 uint64_t access:1; 1423 uint64_t srio:1; 1424#else 1425 uint64_t srio:1; 1426 uint64_t access:1; 1427 uint64_t reserved_2_63:62; 1428#endif 1429 } s; 1430}; 1431 1432union cvmx_sriox_tag_ctrl { 1433 uint64_t u64; 1434 struct cvmx_sriox_tag_ctrl_s { 1435#ifdef __BIG_ENDIAN_BITFIELD 1436 uint64_t reserved_17_63:47; 1437 uint64_t o_clr:1; 1438 uint64_t reserved_13_15:3; 1439 uint64_t otag:5; 1440 uint64_t reserved_5_7:3; 1441 uint64_t itag:5; 1442#else 1443 uint64_t itag:5; 1444 uint64_t reserved_5_7:3; 1445 uint64_t otag:5; 1446 uint64_t reserved_13_15:3; 1447 uint64_t o_clr:1; 1448 uint64_t reserved_17_63:47; 1449#endif 1450 } s; 1451}; 1452 1453union cvmx_sriox_tlp_credits { 1454 uint64_t u64; 1455 struct cvmx_sriox_tlp_credits_s { 1456#ifdef __BIG_ENDIAN_BITFIELD 1457 uint64_t reserved_28_63:36; 1458 uint64_t mbox:4; 1459 uint64_t comp:8; 1460 uint64_t reserved_13_15:3; 1461 uint64_t n_post:5; 1462 uint64_t post:8; 1463#else 1464 uint64_t post:8; 1465 uint64_t n_post:5; 1466 uint64_t reserved_13_15:3; 1467 uint64_t comp:8; 1468 uint64_t mbox:4; 1469 uint64_t reserved_28_63:36; 1470#endif 1471 } s; 1472}; 1473 1474union cvmx_sriox_tx_bell { 1475 uint64_t u64; 1476 struct cvmx_sriox_tx_bell_s { 1477#ifdef __BIG_ENDIAN_BITFIELD 1478 uint64_t reserved_48_63:16; 1479 uint64_t data:16; 1480 uint64_t dest_id:16; 1481 uint64_t reserved_9_15:7; 1482 uint64_t pending:1; 1483 uint64_t reserved_5_7:3; 1484 uint64_t src_id:1; 1485 uint64_t id16:1; 1486 uint64_t reserved_2_2:1; 1487 uint64_t priority:2; 1488#else 1489 uint64_t priority:2; 1490 uint64_t reserved_2_2:1; 1491 uint64_t id16:1; 1492 uint64_t src_id:1; 1493 uint64_t reserved_5_7:3; 1494 uint64_t pending:1; 1495 uint64_t reserved_9_15:7; 1496 uint64_t dest_id:16; 1497 uint64_t data:16; 1498 uint64_t reserved_48_63:16; 1499#endif 1500 } s; 1501}; 1502 1503union cvmx_sriox_tx_bell_info { 1504 uint64_t u64; 1505 struct cvmx_sriox_tx_bell_info_s { 1506#ifdef __BIG_ENDIAN_BITFIELD 1507 uint64_t reserved_48_63:16; 1508 uint64_t data:16; 1509 uint64_t dest_id:16; 1510 uint64_t reserved_8_15:8; 1511 uint64_t timeout:1; 1512 uint64_t error:1; 1513 uint64_t retry:1; 1514 uint64_t src_id:1; 1515 uint64_t id16:1; 1516 uint64_t reserved_2_2:1; 1517 uint64_t priority:2; 1518#else 1519 uint64_t priority:2; 1520 uint64_t reserved_2_2:1; 1521 uint64_t id16:1; 1522 uint64_t src_id:1; 1523 uint64_t retry:1; 1524 uint64_t error:1; 1525 uint64_t timeout:1; 1526 uint64_t reserved_8_15:8; 1527 uint64_t dest_id:16; 1528 uint64_t data:16; 1529 uint64_t reserved_48_63:16; 1530#endif 1531 } s; 1532}; 1533 1534union cvmx_sriox_tx_ctrl { 1535 uint64_t u64; 1536 struct cvmx_sriox_tx_ctrl_s { 1537#ifdef __BIG_ENDIAN_BITFIELD 1538 uint64_t reserved_53_63:11; 1539 uint64_t tag_th2:5; 1540 uint64_t reserved_45_47:3; 1541 uint64_t tag_th1:5; 1542 uint64_t reserved_37_39:3; 1543 uint64_t tag_th0:5; 1544 uint64_t reserved_20_31:12; 1545 uint64_t tx_th2:4; 1546 uint64_t reserved_12_15:4; 1547 uint64_t tx_th1:4; 1548 uint64_t reserved_4_7:4; 1549 uint64_t tx_th0:4; 1550#else 1551 uint64_t tx_th0:4; 1552 uint64_t reserved_4_7:4; 1553 uint64_t tx_th1:4; 1554 uint64_t reserved_12_15:4; 1555 uint64_t tx_th2:4; 1556 uint64_t reserved_20_31:12; 1557 uint64_t tag_th0:5; 1558 uint64_t reserved_37_39:3; 1559 uint64_t tag_th1:5; 1560 uint64_t reserved_45_47:3; 1561 uint64_t tag_th2:5; 1562 uint64_t reserved_53_63:11; 1563#endif 1564 } s; 1565}; 1566 1567union cvmx_sriox_tx_emphasis { 1568 uint64_t u64; 1569 struct cvmx_sriox_tx_emphasis_s { 1570#ifdef __BIG_ENDIAN_BITFIELD 1571 uint64_t reserved_4_63:60; 1572 uint64_t emph:4; 1573#else 1574 uint64_t emph:4; 1575 uint64_t reserved_4_63:60; 1576#endif 1577 } s; 1578}; 1579 1580union cvmx_sriox_tx_status { 1581 uint64_t u64; 1582 struct cvmx_sriox_tx_status_s { 1583#ifdef __BIG_ENDIAN_BITFIELD 1584 uint64_t reserved_32_63:32; 1585 uint64_t s2m_pr3:8; 1586 uint64_t s2m_pr2:8; 1587 uint64_t s2m_pr1:8; 1588 uint64_t s2m_pr0:8; 1589#else 1590 uint64_t s2m_pr0:8; 1591 uint64_t s2m_pr1:8; 1592 uint64_t s2m_pr2:8; 1593 uint64_t s2m_pr3:8; 1594 uint64_t reserved_32_63:32; 1595#endif 1596 } s; 1597}; 1598 1599union cvmx_sriox_wr_done_counts { 1600 uint64_t u64; 1601 struct cvmx_sriox_wr_done_counts_s { 1602#ifdef __BIG_ENDIAN_BITFIELD 1603 uint64_t reserved_32_63:32; 1604 uint64_t bad:16; 1605 uint64_t good:16; 1606#else 1607 uint64_t good:16; 1608 uint64_t bad:16; 1609 uint64_t reserved_32_63:32; 1610#endif 1611 } s; 1612}; 1613 1614#endif 1615