Searched refs:best_parent_rate (Results 1 - 25 of 80) sorted by relevance

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/linux-master/drivers/clk/at91/
H A Dclk-smd.c46 if (req->rate >= req->best_parent_rate) {
47 req->rate = req->best_parent_rate;
51 div = req->best_parent_rate / req->rate;
53 req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1);
57 bestrate = req->best_parent_rate / div;
58 tmp = req->best_parent_rate / (div + 1);
H A Dclk-audio-pll.c251 req->rate, req->best_parent_rate);
258 ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
263 req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
278 unsigned long best_parent_rate; local
306 best_parent_rate = clk_hw_round_rate(pclk,
308 tmp_rate = best_parent_rate / (div * tmp_qd);
312 *parent_rate = best_parent_rate;
318 pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
319 __func__, best_rate, best_parent_rate);
329 unsigned long best_parent_rate local
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/linux-master/drivers/clk/
H A Dclk-multiplier.c66 unsigned long *best_parent_rate,
70 unsigned long orig_parent_rate = *best_parent_rate;
97 *best_parent_rate = orig_parent_rate;
108 *best_parent_rate = parent_rate;
65 __bestmult(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, u8 width, unsigned long flags) argument
H A Dclk-divider.c291 unsigned long *best_parent_rate,
297 unsigned long parent_rate_saved = *best_parent_rate;
305 parent_rate = *best_parent_rate;
326 *best_parent_rate = parent_rate_saved;
334 *best_parent_rate = parent_rate;
340 *best_parent_rate = clk_hw_round_rate(parent, 1);
353 &req->best_parent_rate, table, width, flags);
355 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
374 req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
378 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, di
289 clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *best_parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags) argument
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H A Dclk-si5351.c460 a = rate / req->best_parent_rate;
463 rate = req->best_parent_rate * SI5351_PLL_A_MIN;
465 rate = req->best_parent_rate * SI5351_PLL_A_MAX;
469 lltmp = rate % (req->best_parent_rate);
471 do_div(lltmp, req->best_parent_rate);
488 lltmp = req->best_parent_rate;
493 rate += req->best_parent_rate * a;
498 req->best_parent_rate, rate);
688 req->best_parent_rate = a * rate;
691 a = DIV_ROUND_CLOSEST(req->best_parent_rate, rat
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H A Dclk-composite.c53 req->best_parent_rate = clk_hw_get_rate(parent_hw);
59 &req->best_parent_rate);
102 req->best_parent_rate = tmp_req.best_parent_rate;
130 req->best_parent_rate = tmp_req.best_parent_rate;
H A Dclk-cdce706.c301 __func__, rate, req->best_parent_rate);
303 rational_best_approximation(rate, req->best_parent_rate,
348 __func__, req->best_parent_rate, rate * div);
349 req->best_parent_rate = rate * div;
357 req->rate = req->best_parent_rate / div;
429 req->best_parent_rate = req->rate;
/linux-master/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c92 .best_parent_rate = pllp_rate,
98 pllp_rate = parent.best_parent_rate;
102 req->best_parent_rate = pllp_rate;
107 req->best_parent_rate = rate;
H A Dclk-tegra20-emc.c187 parent_rate = req->best_parent_rate;
200 req->best_parent_rate = parent_rate;
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_mux.c89 unsigned long best_parent_rate = 0, best_rate = 0; local
97 best_parent_rate = clk_hw_get_rate(best_parent);
99 best_parent_rate);
109 best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1,
137 best_parent_rate = parent_rate;
144 best_parent_rate = parent_rate;
154 req->best_parent_rate = best_parent_rate;
H A Dccu_nkm.c24 unsigned long best_rate = 0, best_parent_rate = *parent; local
39 best_parent_rate = tmp_parent;
52 *parent = best_parent_rate;
/linux-master/drivers/clk/rockchip/
H A Dclk-half-divider.c36 unsigned long *best_parent_rate, u8 width,
41 unsigned long parent_rate_saved = *best_parent_rate;
49 parent_rate = *best_parent_rate;
72 *best_parent_rate = parent_rate_saved;
83 *best_parent_rate = parent_rate;
89 *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
35 clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, u8 width, unsigned long flags) argument
/linux-master/drivers/clk/imx/
H A Dclk-pfdv2.c107 req->best_parent_rate
110 unsigned long best_parent_rate = req->best_parent_rate; local
132 best_parent_rate = parent_rates[i];
136 req->best_parent_rate = best_parent_rate;
/linux-master/drivers/clk/actions/
H A Dowl-factor.c68 unsigned long *best_parent_rate)
72 unsigned long parent_rate_saved = *best_parent_rate;
79 parent_rate = *best_parent_rate;
96 *best_parent_rate = parent_rate_saved;
106 *best_parent_rate = parent_rate;
112 *best_parent_rate = clk_hw_round_rate(
66 owl_clk_val_best(const struct owl_factor_hw *factor_hw, struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate) argument
H A Dowl-composite.c63 req->rate, &req->best_parent_rate);
97 req->rate, &req->best_parent_rate);
/linux-master/drivers/clk/meson/
H A Dclk-dualdiv.c96 setting = __dualdiv_get_setting(req->rate, req->best_parent_rate,
99 req->rate = __dualdiv_param_to_rate(req->best_parent_rate,
103 req->best_parent_rate);
H A Dclk-mpll.c97 params_from_rate(req->rate, req->best_parent_rate, &sdm, &n2,
100 rate = rate_from_params(req->best_parent_rate, sdm, n2);
H A Dclk-pll.c253 ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
258 round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
269 frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
270 req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
H A Dsclk-div.c106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
107 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
/linux-master/drivers/clk/ti/
H A Ddivider.c169 unsigned long *best_parent_rate)
174 unsigned long parent_rate_saved = *best_parent_rate;
182 parent_rate = *best_parent_rate;
204 *best_parent_rate = parent_rate_saved;
213 *best_parent_rate = parent_rate;
219 *best_parent_rate =
168 ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate) argument
H A Ddpll44xx.c219 &req->best_parent_rate);
223 req->best_parent_rate = req->rate;
/linux-master/drivers/clk/qcom/
H A Dclk-krait.c102 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
103 req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
H A Dclk-hfpll.c143 rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate;
145 rrate -= req->best_parent_rate;
H A Dclk-rcg2.c257 req->best_parent_rate = rate;
602 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
604 if (req->best_parent_rate == 810000000)
613 if ((req->best_parent_rate < (request - delta)) ||
614 (req->best_parent_rate > (request + delta)))
622 req->rate = calc_rate(req->best_parent_rate,
656 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
713 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
794 req->best_parent_rate = src_rate;
897 req->rate = req->best_parent_rate
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/linux-master/sound/soc/codecs/
H A Dtlv320aic32x4-clk.c213 ret = clk_aic32x4_pll_calc_muldiv(&settings, req->rate, req->best_parent_rate);
217 req->rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate);
336 divisor = DIV_ROUND_UP(req->best_parent_rate, req->rate);
340 req->rate = DIV_ROUND_UP(req->best_parent_rate, divisor);

Completed in 207 milliseconds

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