#
f7b7d301 |
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01-Sep-2023 |
Devi Priya <quic_devipriy@quicinc.com> |
clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequencies If the parent clock rate is greater than unsigned long max/2 then integer overflow happens when calculating the clock rate on 32-bit systems. As RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 which will overflow the unsigned long max value. Hence, replace the common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac call. Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230901073640.4973-1-quic_devipriy@quicinc.com [bjorn: Also drop unnecessary {} around single statements] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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#
a0e0ec74 |
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17-May-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
clk: qcom: rcg2: Make hw_clk_ctrl toggleable Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they host. This allows the clocks to be turned on automatically when a downstream branch tries to change rate or config. Make it togglable so that we can utilize this. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-2-4f40e282af1d@linaro.org
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#
af1e62f2 |
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16-Aug-2022 |
Maxime Ripard <maxime@cerno.tech> |
clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d The gfx3d clock is hand-crafting its own clk_rate_request in clk_gfx3d_determine_rate to pass to the parent of that clock. However, since the clk_rate_request is zero'd at creation, it will have a max_rate of 0 which will break any code depending on the clock boundaries. That includes the recent commit 948fb0969eae ("clk: Always clamp the rounded rate") which will clamp the rate given to clk_round_rate() to the current clock boundaries. For the gfx3d clock, it means that since both the min_rate and max_rate fields are set at zero, clk_round_rate() now always return 0. Let's initialize the min_rate and max_rate fields properly for that clock. Fixes: 948fb0969eae ("clk: Always clamp the rounded rate") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-25-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c5d2c96b |
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18-Aug-2022 |
Christian Marangi <ansuelsmth@gmail.com> |
clk: qcom: clk-rcg2: add rcg2 mux ops An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
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#
d0696770 |
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12-Jun-2022 |
Nikita Travkin <nikita@trvn.ru> |
clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register Sometimes calculation of d value may result in 0 because of the rounding after integer division. This causes the following error: [ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration. [ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc Make sure that D value is never zero. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin <nikita@trvn.ru> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru
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#
bdafb609 |
|
12-Jun-2022 |
Nikita Travkin <nikita@trvn.ru> |
clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled. In cases when MND is not enabled (e.g. when only Half Integer Divider is used), setting D registers makes no effect. Fail instead of making ineffective write. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin <nikita@trvn.ru> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220612145955.385787-2-nikita@trvn.ru
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#
703db1f5 |
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26-Apr-2022 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
clk: qcom: rcg2: Cache CFG register updates for parked RCGs As GDSCs are turned on and off some associated clocks are momentarily enabled for house keeping purposes. For this, and similar, purposes the "shared RCGs" will park the RCG on a source clock which is known to be available. When the RCG is parked, a safe clock source will be selected and committed, then the original source would be written back and upon enable the change back to the unparked source would be committed. But starting with SM8350 this fails, as the value in CFG is committed by the GDSC handshake and without a ticking parent the GDSC enablement will time out. This becomes a concrete problem if the runtime supended state of a device includes disabling such rcg's parent clock. As the device attempts to power up the domain again the rcg will fail to enable and hence the GDSC enablement will fail, preventing the device from returning from the suspended state. This can be seen in e.g. the display stack during probe on SM8350. To avoid this problem, the software needs to ensure that the RCG is configured to a active parent clock while it is disabled. This is done by caching the CFG register content while the shared RCG is parked on this safe source. Writes to M, N and D registers are committed as they are requested. New helpers for get_parent() and recalc_rate() are extracted from their previous implementations and __clk_rcg2_configure() is modified to allow it to operate on the cached value. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org
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#
d968fda3 |
|
19-Apr-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
clk: qcom: clk-rcg2: fix gfx3d frequency calculation Since the commit 948fb0969eae ("clk: Always clamp the rounded rate"), the clk_core_determine_round_nolock() would clamp the requested rate between min and max rates from the rate request. Normally these fields would be filled by clk_core_get_boundaries() called from clk_round_rate(). However clk_gfx3d_determine_rate() uses a manually crafted rate request, which did not have these fields filled. Thus the requested frequency would be clamped to 0, resulting in weird frequencies being requested from the hardware. Fix this by filling min_rate and max_rate to the values valid for the respective PLLs (0 and ULONG_MAX). Fixes: 948fb0969eae ("clk: Always clamp the rounded rate") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220419235447.1586192-1-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reported-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
b527358c |
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27-Feb-2022 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: clk-rcg2: Update the frac table for pixel clock Support the new numerator and denominator for pixel clock on SM8350 and support rgb101010, RGB888 use cases on SM8450. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220227175536.3131-2-tdas@codeaurora.org
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#
58922910 |
|
27-Feb-2022 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: clk-rcg2: Update logic to calculate D value for RCG The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org
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#
7f891faf |
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24-Apr-2021 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: clk-rcg2: Add support for duty-cycle for RCG The root clock generators with MND divider has the capability to support change in duty-cycle by updating the 'D'. Add the clock ops which would check all the boundary conditions and enable setting the desired duty-cycle as per the consumer. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1619334502-9880-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Remove _val everywhere] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
0ae67123 |
|
02-Mar-2021 |
Marijn Suijten <marijn.suijten@somainline.org> |
clk: qcom: rcg2: Rectify clk_gfx3d rate rounding without mux division In case the mux is not divided parent_req was mistakenly not assigned to leading __clk_determine_rate to determine the best frequency setting for a requested rate of 0, resulting in the msm8996 platform not booting. Rectify this by refactoring the logic to unconditionally assign to parent_req.rate with the clock rate the caller is expecting. Fixes: 7cbb78a99db6 ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers") Reported-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210302234106.3418665-1-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
7cbb78a9 |
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13-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers The function clk_gfx3d_determine_rate is selecting different PLLs to manage the GFX3D clock source in a special way: this one needs to be ping-pong'ed on different PLLs to ensure stability during frequency switching (set a PLL rate, let it stabilize, switch the RCG to the new PLL) and fast frequency transitions. This technique is currently being used in the MSM8996 SoC and the function was assuming that the parents were always at a specific index in the parents list, which is TRUE, if we use this only on the MSM8996 MMCC. Unfortunately, MSM8996 is not the only SoC that needs to ping-pong the graphics RCG, so choices are: 1. Make new special ops just to hardcode *again* other indexes, creating code duplication for (imo) no reason; or 2. Generalize this function, so that it becomes usable for a range of SoCs with slightly different ping-pong configuration. In this commit, the second road was taken: define a new "special" struct clk_rcg2_gfx3d, containing the ordered list of parents to ping-pong the graphics clock on, and the "regular" rcg2 clock structure in order to generalize the clk_gfx3d_determine_rate function and make it working for other SoCs. As for the function itself it is left with the assumption that we need to ping-pong over three parents. The reasons for this are: 1. The initial model was MSM8996, which has 3 parents for the graphics clock pingpong; 2. The other example that was taken into consideration is the SDM630/636/660 SoC gpu clock controller, which is ping-ponging over two dynamic clocked and one fixed clock PLL. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-6-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Grow some local variables, drop do_div() usage in favor of plain division, we're not dealing with a u64 here] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
355a7d75 |
|
16-Sep-2020 |
Stephen Boyd <swboyd@chromium.org> |
clk: qcom: dispcc: Update DP clk ops for phy design The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-10-swboyd@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
908b0501 |
|
03-Feb-2020 |
Douglas Anderson <dianders@chromium.org> |
clk: qcom: rcg2: Don't crash if our parent can't be found; return an error When I got my clock parenting slightly wrong I ended up with a crash that looked like this: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... pc : clk_hw_get_rate+0x14/0x44 ... Call trace: clk_hw_get_rate+0x14/0x44 _freq_tbl_determine_rate+0x94/0xfc clk_rcg2_determine_rate+0x2c/0x38 clk_core_determine_round_nolock+0x4c/0x88 clk_core_round_rate_nolock+0x6c/0xa8 clk_core_round_rate_nolock+0x9c/0xa8 clk_core_set_rate_nolock+0x70/0x180 clk_set_rate+0x3c/0x6c of_clk_set_defaults+0x254/0x360 platform_drv_probe+0x28/0xb0 really_probe+0x120/0x2dc driver_probe_device+0x64/0xfc device_driver_attach+0x4c/0x6c __driver_attach+0xac/0xc0 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0xfc/0x1d0 driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 msm_drm_register+0x5c/0x60 ... It turned out that clk_hw_get_parent_by_index() was returning NULL and we weren't checking. Let's check it so that we don't crash. Fixes: ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lkml.kernel.org/r/20200203103049.v4.1.I7487325fe8e701a68a07d3be8a6a4b571eca9cfa@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
21e157c6 |
|
28-Jan-2020 |
Stephen Boyd <sboyd@kernel.org> |
clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq() The DFS frequency table logic overwrites 'cfg' while detecting the parent clk and then later on in clk_rcg2_dfs_populate_freq() we use that same variable to figure out the mode of the clk, either MND or not. Add a new variable to hold the parent clk bit so that 'cfg' is left untouched for use later. This fixes problems in detecting the supported frequencies for any clks in DFS mode. Fixes: cc4f6944d0e3 ("clk: qcom: Add support for RCG to register for DFS") Reported-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200128193329.45635-1-sboyd@kernel.org Tested-by: Rajendra Nayak <rnayak@codeaurora.org>
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#
cddf1f82 |
|
31-Jul-2019 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: rcg2: Add support for display port clock ops New display port clock ops supported for display port clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
efd164b5 |
|
31-Oct-2019 |
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> |
clk: qcom: Allow constant ratio freq tables for rcg Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just some constant ratio from the input across the entire frequency range. It would be great if we could specify the frequency table as a single entry constant ratio instead of a long list, ie: { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, { } So, lets support that. We need to fix a corner case in qcom_find_freq() where if the freq table is non-null, but has no frequencies, we end up returning an "entry" before the table array, which is bad. Then, we need ignore the freq from the table, and instead base everything on the requested freq. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
57b2364d |
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25-Oct-2019 |
YueHaibing <yuehaibing@huawei.com> |
clk: qcom: remove unneeded semicolon remove unneeded semicolon. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191025093332.27592-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
21ea4b62 |
|
08-May-2019 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: rcg: Return failure for RCG update In case of update config failure, return -EBUSY, so that consumers could handle the failure gracefully. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c4214413 |
|
15-Aug-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: qcom: Remove error prints from DFS registration These aren't useful and they reference the init structure name. Let's just drop them. Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815160020.183334-5-sboyd@kernel.org Acked-by: Taniya Das <tdas@codeaurora.org>
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#
96dc791d |
|
11-Feb-2019 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD RCGR register. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
2bdb2a1c |
|
30-Aug-2018 |
Douglas Anderson <dianders@chromium.org> |
clk: qcom: Allocate space for NULL terimation in DFS table The table allocated in clk_rcg2_dfs_populate_freq_table() is eventually iterated over by qcom_find_freq() which assumes that the table is NULL terminated. Allocate one extra space in the array for the NULL termination. Initting of the NULL termination is implicit due to kcalloc(). Fixes: cc4f6944d0e3 ("clk: qcom: Add support for RCG to register for DFS") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
cc4f6944 |
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10-Aug-2018 |
Taniya Das <tdas@codeaurora.org> |
clk: qcom: Add support for RCG to register for DFS Dynamic Frequency switch is a feature of clock controller by which request from peripherals allows automatic switching frequency of input clock without SW intervention. There are various performance levels associated with a root clock. When the input performance state changes, the source clocks and division ratios of the new performance state are loaded on to RCG via HW and the RCG switches to new clock frequency when the RCG is in DFS HW enabled mode. Register the root clock generators(RCG) to switch to use the dfs clock ops in the cases where DFS is enabled. The clk_round_rate() called by the clock consumer would invoke the dfs determine clock ops and would read the DFS performance level registers to identify all the frequencies supported and update the frequency table. The DFS clock consumers would maintain these frequency mapping and request the desired performance levels. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Rework registration logic to stop copying, change recalc_rate() to index directly into the table if possible and fallback to calculating on the fly with an assumed correct parent] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c7d2a0eb |
|
13-Apr-2018 |
Evan Green <evgreen@chromium.org> |
clk: qcom: Base rcg parent rate off plan frequency _freq_tbl_determine_rate uses the pre_div found in the clock plan multiplied by the requested rate from the caller to determine the best parent rate to set. If the requested rate is not exactly equal to the rate that was found in the clock plan, then using the requested rate in parent rate calculations is incorrect. For instance, if 150MHz was requested, but 200MHz was the match found, and that plan had a pre_div of 3, then the parent should be set to 600MHz, not 450MHz. Signed-off-by: Evan Green <evgreen@chromium.org> Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
7ef6f118 |
|
07-May-2018 |
Amit Nischal <anischal@codeaurora.org> |
clk: qcom: Configure the RCGs to a safe source as needed For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
bdc3bbdd |
|
07-Mar-2018 |
Amit Nischal <anischal@codeaurora.org> |
clk: qcom: Clear hardware clock control bit of RCG For upcoming targets like sdm845, POR value of the hardware clock control bit is set for most of root clocks which needs to be cleared for software to be able to control. For older targets like MSM8996, this bit is reserved bit and having POR value as 0 so this patch will work for the older targets too. So update the configuration mask to take care of the same to clear hardware clock control bit. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a49580ec |
|
24-Aug-2017 |
Georgi Djakov <georgi.djakov@linaro.org> |
clk: qcom: Remove unused RCG ops The RCGs ops for shared branches are not used now, so remove it. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
081ba802 |
|
20-Nov-2016 |
Rajendra Nayak <rnayak@codeaurora.org> |
clk: qcom: Add rcg ops to return floor value closest to the requested rate The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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55213e1a |
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30-Nov-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Add gfx3d ping-pong PLL frequency switching The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2, MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624 MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To make switching frequencies faster, we ping-pong between MMPLL2 and MMPLL8 when we're switching between frequencies that aren't the maximum. Implement custom rcg clk ops for this type of frequency switching. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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d042877a |
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17-Sep-2015 |
Georgi Djakov <georgi.djakov@linaro.org> |
clk: qcom: Add support for RCGs with shared branches Some root clock generators may have child branches that are controlled by different CPUs. These RCGs require some special operations: - some enable bits have to be toggled when we set the rate; - if RCG is disabled we only cache the rate and set it later when enabled; - when the RCG is disabled, the mux is set to the safe source; Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> [sboyd@codeaurora.org: Simplify recalc_rate implementation] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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8ee9c7de |
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10-Apr-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Allow clk_set_parent() to work on display clocks Sometimes the display driver may want to change the parent PLL of the display clocks (byte and pixel clocks) depending on the use-case. Currently the parent is fixed by means of having a frequency table with one entry that chooses a particular parent. Remove this restriction and use the parent the clock is configured for in the hardware during clk_set_rate(). This requires consumers to rely on the default parent or to configure the parent with clk_set_parent()/assigned-clock-parents on the clocks before calling clk_set_rate(). Tested-by: Archit Taneja <architt@codeaurora.org> Cc: Hai Li <hali@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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ac269395 |
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30-Jul-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Convert to clk_hw based provider APIs We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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98d8a60e |
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29-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: Convert __clk_get_flags() to clk_hw_get_flags() Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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497295af |
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25-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: Replace __clk_get_num_parents with clk_hw_get_num_parents() Mostly converted with the following semantic patch: @@ struct clk_hw *E; @@ -__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E) Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chao Xie <chao.xie@marvell.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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0817b62c |
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07-Jul-2015 |
Boris Brezillon <bbrezillon@kernel.org> |
clk: change clk_ops' ->determine_rate() prototype Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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6d451367 |
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25-Jun-2015 |
Hai Li <hali@codeaurora.org> |
clk: qcom: Use parent rate when set rate to pixel RCG clock Since the parent rate has been recalculated, pixel RCG clock should rely on it to find the correct M/N values during set_rate, instead of calling __clk_round_rate() to its parent again. Signed-off-by: Hai Li <hali@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Fixes: 99cbd064b059 ("clk: qcom: Support display RCG clocks") [sboyd@codeaurora.org: Silenced unused parent variable warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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2f272e7b |
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07-Apr-2015 |
Georgi Djakov <georgi.djakov@linaro.org> |
clk: qcom: Fix parent_map translations When we introduced the parent_map tables, we missed to update some of the functions where mapping is translated. Fix this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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293d2e97 |
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20-Mar-2015 |
Georgi Djakov <georgi.djakov@linaro.org> |
clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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7f218978 |
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20-Mar-2015 |
Georgi Djakov <georgi.djakov@linaro.org> |
clk: qcom: Fix clk_get_parent function return value According to the common clock framework API, the clk_get_parent() function should return u8. Currently we are returning negative values on error. Fix this and use the default parent in case of an error. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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0b21503d |
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04-Mar-2015 |
Archit Taneja <architt@codeaurora.org> |
clk: qcom: fix RCG M/N counter configuration Currently, a RCG's M/N counter (used for fraction division) is set to either 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether the corresponding rcg struct has a mnd field specified and a non-zero N. In the case where M and N are the same value, the M/N counter is still enabled by code even though no division takes place. Leaving the RCG in such a state can result in improper behavior. This was observed with the DSI pixel clock RCG when M and N were both set to 1. Add an additional check (M != N) to enable the M/N counter only when it's needed for fraction division. Signed-off-by: Archit Taneja <architt@codeaurora.org> Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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1c8e6004 |
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22-Jan-2015 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
clk: Add rate constraints to clocks Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
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646cafc6 |
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02-Dec-2014 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
clk: Change clk_ops->determine_rate to return a clk_hw as the best parent This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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50c6a503 |
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04-Sep-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Consolidate frequency finding logic There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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99cbd064 |
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16-May-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Support display RCG clocks Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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9d011f3b |
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16-May-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Return highest rate when round_rate() exceeds plan Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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aa014149 |
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16-May-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Fix clk_rcg2_is_enabled() check If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic. Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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bcd61c0f |
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15-Jan-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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