clk: imx: Fix the build break when clk-imx8ulp build as module

Export the necessary symbols to fix the build break when clk-imx8ulp
build as module

Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210917061629.3798360-1-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx: Update the pfdv2 for 8ulp specific support

On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be
set and according to the laest RM, the PFD divider value range
seems will be changed in the future, so update the pfdv2 to
include the specific support for i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx: disable the pfd when set pfdv2 clock rate

It is possible that a PFD is enabled in HW but not in SW. That
means the enable count & prepare count of the PFD clock is '0',
so the 'CLK_SET_RATE' flag can do nothing when the rate is changed
while the PFD is hw enabled. In order to safely change the pfd
rate, we can disable the PFD directly if it is hw enabled but not
used by SW end user.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-7-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx: Fix and update kerneldoc

Fix and add missing kerneldoc to fix compile warnings like:

drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd'
drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

clk: imx: pfdv2: determine best parent rate

pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP
Datasheet defines two best PLL rate and pfd frac.

Per Datasheel
All PLLs on i.MX 7ULP either have VCO base frequency of
480 MHz or 528 MHz. So when determine best rate, we also
determine best parent rate which could match the requirement.

For some reason the current parent might not be 480MHz or 528MHz,
so we still take current parent rate as a choice.

And we also enable flag CLK_SET_RATE_PARENT to let parent rate
to be configured.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

clk: imx: pfdv2: switch to use determine_rate

Per clk_ops, compared with round_rate, determine_rate could optionally
support the parent clock that should be used to provide the clock rate.

In this patch, the parent clock is just parent->rate as round_rate.

The following patch will calculate the best parent clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

clk: imx: Fix division by zero warning on pfdv2

Fix below division by zero warning:

[ 3.176443] Division by zero in kernel.
[ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124
[ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree)
[ 3.197821] Workqueue: events dbs_work_handler
[ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14)
[ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110)
[ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18)
[ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac)
[ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698)
[ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698)
[ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278)
[ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64)
[ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4)
[ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514)
[ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c)
[ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c)
[ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704)
[ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574)
[ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148)
[ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
[ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8)
[ 3.345314] 5fa0: 00000000 00000000 00000000 00000000
[ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based

Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be
more obvious it is clk_hw based.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

clk: Remove io.h from clk-provider.h

Now that we've gotten rid of clk_readl() we can remove io.h from the
clk-provider header and push out the io.h include to any code that isn't
already including the io.h header but using things like readl/writel,
etc.

Found with this grep:

git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \
xargs git grep -l \
-e '\<__iowrite32_copy\>' --or \
-e '\<__ioread32_copy\>' --or \
-e '\<__iowrite64_copy\>' --or \
-e '\<ioremap_page_range\>' --or \
-e '\<ioremap_huge_init\>' --or \
-e '\<arch_ioremap_pud_supported\>' --or \
-e '\<arch_ioremap_pmd_supported\>' --or \
-e '\<devm_ioport_map\>' --or \
-e '\<devm_ioport_unmap\>' --or \
-e '\<IOMEM_ERR_PTR\>' --or \
-e '\<devm_ioremap\>' --or \
-e '\<devm_ioremap_nocache\>' --or \
-e '\<devm_ioremap_wc\>' --or \
-e '\<devm_iounmap\>' --or \
-e '\<devm_ioremap_release\>' --or \
-e '\<devm_memremap\>' --or \
-e '\<devm_memunmap\>' --or \
-e '\<__devm_memremap_pages\>' --or \
-e '\<pci_remap_cfgspace\>' --or \
-e '\<arch_has_dev_port\>' --or \
-e '\<arch_phys_wc_add\>' --or \
-e '\<arch_phys_wc_del\>' --or \
-e '\<memremap\>' --or \
-e '\<memunmap\>' --or \
-e '\<arch_io_reserve_memtype_wc\>' --or \
-e '\<arch_io_free_memtype_wc\>' --or \
-e '\<__io_aw\>' --or \
-e '\<__io_pbw\>' --or \
-e '\<__io_paw\>' --or \
-e '\<__io_pbr\>' --or \
-e '\<__io_par\>' --or \
-e '\<__raw_readb\>' --or \
-e '\<__raw_readw\>' --or \
-e '\<__raw_readl\>' --or \
-e '\<__raw_readq\>' --or \
-e '\<__raw_writeb\>' --or \
-e '\<__raw_writew\>' --or \
-e '\<__raw_writel\>' --or \
-e '\<__raw_writeq\>' --or \
-e '\<readb\>' --or \
-e '\<readw\>' --or \
-e '\<readl\>' --or \
-e '\<readq\>' --or \
-e '\<writeb\>' --or \
-e '\<writew\>' --or \
-e '\<writel\>' --or \
-e '\<writeq\>' --or \
-e '\<readb_relaxed\>' --or \
-e '\<readw_relaxed\>' --or \
-e '\<readl_relaxed\>' --or \
-e '\<readq_relaxed\>' --or \
-e '\<writeb_relaxed\>' --or \
-e '\<writew_relaxed\>' --or \
-e '\<writel_relaxed\>' --or \
-e '\<writeq_relaxed\>' --or \
-e '\<readsb\>' --or \
-e '\<readsw\>' --or \
-e '\<readsl\>' --or \
-e '\<readsq\>' --or \
-e '\<writesb\>' --or \
-e '\<writesw\>' --or \
-e '\<writesl\>' --or \
-e '\<writesq\>' --or \
-e '\<inb\>' --or \
-e '\<inw\>' --or \
-e '\<inl\>' --or \
-e '\<outb\>' --or \
-e '\<outw\>' --or \
-e '\<outl\>' --or \
-e '\<inb_p\>' --or \
-e '\<inw_p\>' --or \
-e '\<inl_p\>' --or \
-e '\<outb_p\>' --or \
-e '\<outw_p\>' --or \
-e '\<outl_p\>' --or \
-e '\<insb\>' --or \
-e '\<insw\>' --or \
-e '\<insl\>' --or \
-e '\<outsb\>' --or \
-e '\<outsw\>' --or \
-e '\<outsl\>' --or \
-e '\<insb_p\>' --or \
-e '\<insw_p\>' --or \
-e '\<insl_p\>' --or \
-e '\<outsb_p\>' --or \
-e '\<outsw_p\>' --or \
-e '\<outsl_p\>' --or \
-e '\<ioread8\>' --or \
-e '\<ioread16\>' --or \
-e '\<ioread32\>' --or \
-e '\<ioread64\>' --or \
-e '\<iowrite8\>' --or \
-e '\<iowrite16\>' --or \
-e '\<iowrite32\>' --or \
-e '\<iowrite64\>' --or \
-e '\<ioread16be\>' --or \
-e '\<ioread32be\>' --or \
-e '\<ioread64be\>' --or \
-e '\<iowrite16be\>' --or \
-e '\<iowrite32be\>' --or \
-e '\<iowrite64be\>' --or \
-e '\<ioread8_rep\>' --or \
-e '\<ioread16_rep\>' --or \
-e '\<ioread32_rep\>' --or \
-e '\<ioread64_rep\>' --or \
-e '\<iowrite8_rep\>' --or \
-e '\<iowrite16_rep\>' --or \
-e '\<iowrite32_rep\>' --or \
-e '\<iowrite64_rep\>' --or \
-e '\<__io_virt\>' --or \
-e '\<pci_iounmap\>' --or \
-e '\<virt_to_phys\>' --or \
-e '\<phys_to_virt\>' --or \
-e '\<ioremap_uc\>' --or \
-e '\<ioremap\>' --or \
-e '\<__ioremap\>' --or \
-e '\<iounmap\>' --or \
-e '\<ioremap\>' --or \
-e '\<ioremap_nocache\>' --or \
-e '\<ioremap_uc\>' --or \
-e '\<ioremap_wc\>' --or \
-e '\<ioremap_wc\>' --or \
-e '\<ioremap_wt\>' --or \
-e '\<ioport_map\>' --or \
-e '\<ioport_unmap\>' --or \
-e '\<ioport_map\>' --or \
-e '\<ioport_unmap\>' --or \
-e '\<xlate_dev_kmem_ptr\>' --or \
-e '\<xlate_dev_mem_ptr\>' --or \
-e '\<unxlate_dev_mem_ptr\>' --or \
-e '\<virt_to_bus\>' --or \
-e '\<bus_to_virt\>' --or \
-e '\<memset_io\>' --or \
-e '\<memcpy_fromio\>' --or \
-e '\<memcpy_toio\>'

I also reordered a couple includes when they weren't alphabetical and
removed clk.h from kona, replacing it with clk-provider.h because
that driver doesn't use clk consumer APIs.

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Cc: Chris Zankel <chris@zankel.net>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: imx: correct pfdv2 gate_bit/vld_bit operations

The operations of pfdv2 gate_bit/valid_bit are incorrect,
they are defined as u8 for bit offset, but gate_bit is
actually assigned as mask which could be 32 bit long and
it causes overflow, and vld_bit is assigned as bit offset
based on incorrect gate_bit value, it causes incorrect
pfd clock gate status in clock tree, this patch fixes the
issue by assigning them as correct bit offset.

Fixes: 9fcb6be3b6c9 ("clk: imx: add pfdv2 support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.

NOTE pfdv2 can only be operated when clk is gated.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>