| /linux-master/drivers/gpu/drm/nouveau/dispnv50/ |
| H A D | base.c | 33 } bases[] = { local
46 cid = nvif_mclass(&disp->disp->object, bases);
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw);
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| /linux-master/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 131 u32 bases[CLKRST_MAX]; local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) {
151 bases[i] = r.start;
303 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
307 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
311 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
315 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
319 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
323 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
327 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDE
[all...] |
| /linux-master/include/linux/ |
| H A D | posix-timers.h | 91 pct->bases[0].nextevt = U64_MAX;
92 pct->bases[1].nextevt = U64_MAX;
93 pct->bases[2].nextevt = U64_MAX;
101 pct->bases[CPUCLOCK_SCHED].nextevt = runtime;
117 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
|
| H A D | posix-timers_types.h | 48 * @bases: Base container for posix CPU clocks
57 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member in struct:posix_cputimers
|
| /linux-master/drivers/gpu/host1x/ |
| H A D | syncpt.c | 26 struct host1x_syncpt_base *bases = host->bases; local
30 if (!bases[i].requested)
36 bases[i].requested = true;
37 return &bases[i];
282 struct host1x_syncpt_base *bases; local
291 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases),
293 if (!bases)
302 bases[
[all...] |
| H A D | dev.h | 100 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
136 struct host1x_syncpt_base *bases; member in struct:host1x
|
| /linux-master/drivers/iommu/ |
| H A D | rockchip-iommu.c | 107 void __iomem **bases; member in struct:rk_iommu
349 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
369 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
379 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
391 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
403 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
428 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
449 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
470 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
491 rk_iommu_read(iommu->bases[
[all...] |
| /linux-master/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-nvidia.c | 36 void __iomem *bases[MAX_SMMU_INSTANCES]; member in struct:nvidia_smmu
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift);
324 nvidia_smmu->bases[0] = smmu->base;
332 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res);
333 if (IS_ERR(nvidia_smmu->bases[i]))
334 return ERR_CAST(nvidia_smmu->bases[i]);
|
| /linux-master/arch/x86/boot/ |
| H A D | early_serial_console.c | 77 static const int bases[] = { 0x3f8, 0x2f8 }; local
86 port = bases[idx];
|
| /linux-master/kernel/time/ |
| H A D | posix-cpu-timers.c | 28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC;
35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
154 return !(~pct->bases[CPUCLOCK_PROF].nextevt |
155 ~pct->bases[CPUCLOCK_VIRT].nextevt |
156 ~pct->bases[CPUCLOCK_SCHED].nextevt);
422 return tsk->posix_cputimers.bases + clkidx;
424 return tsk->signal->posix_cputimers.bases + clkidx;
533 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead);
534 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead);
535 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHE
[all...] |
| H A D | tick-internal.h | 191 void clock_was_set(unsigned int bases);
|
| H A D | hrtimer.c | 62 * The timer bases:
64 * There are more clockids than hrtimer bases. Thus, we index
65 * into the timer bases by the hrtimer_base_type enum. When trying
543 * the clock bases so the result might be negative. Fix it up
558 * When a softirq is pending, we can ignore the HRTIMER_ACTIVE_SOFT bases,
560 * hrtimer_run_softirq(), hrtimer_update_softirq_timer() will re-add these bases.
562 * Therefore softirq values are those from the HRTIMER_ACTIVE_SOFT clock bases.
603 * soft bases. They will be handled in the already raised soft
862 * clock bases and reprogram the clock event device.
885 * bases
948 clock_was_set(unsigned int bases) argument
[all...] |
| /linux-master/drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_scaler.c | 155 static unsigned int bases[] = { local
163 scaler_write(src_buf->dma_addr[i], bases[i]);
218 static unsigned int bases[] = { local
226 scaler_write(dst_buf->dma_addr[i], bases[i]);
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| /linux-master/arch/x86/kernel/ |
| H A D | early_printk.c | 162 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; local
169 early_serial_base = bases[port];
|
| /linux-master/drivers/net/wireless/broadcom/b43/ |
| H A D | pio.c | 82 static const u16 bases[] = { local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases));
106 return bases[index];
|
| /linux-master/sound/pci/hda/ |
| H A D | hda_proc.c | 249 static const char * const bases[7] = { local
266 return bases[cfg & 0x0f];
|
| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_cs.c | 56 /* mmio bases table *must* be sorted in reverse graphics_ver order */
344 const struct engine_mmio_base *bases)
349 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
353 GEM_BUG_ON(!bases[i].base);
355 return bases[i].base;
343 __engine_mmio_base(struct drm_i915_private *i915, const struct engine_mmio_base *bases) argument
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| /linux-master/drivers/firmware/cirrus/ |
| H A D | cs_dsp.c | 1955 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; local
1957 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases);
|