1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * IOMMU API for Rockchip 4 * 5 * Module Authors: Simon Xue <xxm@rock-chips.com> 6 * Daniel Kurtz <djkurtz@chromium.org> 7 */ 8 9#include <linux/clk.h> 10#include <linux/compiler.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/dma-mapping.h> 14#include <linux/errno.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/iommu.h> 18#include <linux/iopoll.h> 19#include <linux/list.h> 20#include <linux/mm.h> 21#include <linux/init.h> 22#include <linux/of.h> 23#include <linux/of_platform.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26#include <linux/slab.h> 27#include <linux/spinlock.h> 28 29/** MMU register offsets */ 30#define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ 31#define RK_MMU_STATUS 0x04 32#define RK_MMU_COMMAND 0x08 33#define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ 34#define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ 35#define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ 36#define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ 37#define RK_MMU_INT_MASK 0x1C /* IRQ enable */ 38#define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ 39#define RK_MMU_AUTO_GATING 0x24 40 41#define DTE_ADDR_DUMMY 0xCAFEBABE 42 43#define RK_MMU_POLL_PERIOD_US 100 44#define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 45#define RK_MMU_POLL_TIMEOUT_US 1000 46 47/* RK_MMU_STATUS fields */ 48#define RK_MMU_STATUS_PAGING_ENABLED BIT(0) 49#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 50#define RK_MMU_STATUS_STALL_ACTIVE BIT(2) 51#define RK_MMU_STATUS_IDLE BIT(3) 52#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 53#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 54#define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) 55 56/* RK_MMU_COMMAND command values */ 57#define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 58#define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 59#define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 60#define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 61#define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 62#define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 63#define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ 64 65/* RK_MMU_INT_* register fields */ 66#define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 67#define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 68#define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) 69 70#define NUM_DT_ENTRIES 1024 71#define NUM_PT_ENTRIES 1024 72 73#define SPAGE_ORDER 12 74#define SPAGE_SIZE (1 << SPAGE_ORDER) 75 76 /* 77 * Support mapping any size that fits in one page table: 78 * 4 KiB to 4 MiB 79 */ 80#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 81 82struct rk_iommu_domain { 83 struct list_head iommus; 84 u32 *dt; /* page directory table */ 85 dma_addr_t dt_dma; 86 spinlock_t iommus_lock; /* lock for iommus list */ 87 spinlock_t dt_lock; /* lock for modifying page directory table */ 88 89 struct iommu_domain domain; 90}; 91 92/* list of clocks required by IOMMU */ 93static const char * const rk_iommu_clocks[] = { 94 "aclk", "iface", 95}; 96 97struct rk_iommu_ops { 98 phys_addr_t (*pt_address)(u32 dte); 99 u32 (*mk_dtentries)(dma_addr_t pt_dma); 100 u32 (*mk_ptentries)(phys_addr_t page, int prot); 101 u64 dma_bit_mask; 102 gfp_t gfp_flags; 103}; 104 105struct rk_iommu { 106 struct device *dev; 107 void __iomem **bases; 108 int num_mmu; 109 int num_irq; 110 struct clk_bulk_data *clocks; 111 int num_clocks; 112 bool reset_disabled; 113 struct iommu_device iommu; 114 struct list_head node; /* entry in rk_iommu_domain.iommus */ 115 struct iommu_domain *domain; /* domain to which iommu is attached */ 116}; 117 118struct rk_iommudata { 119 struct device_link *link; /* runtime PM link from IOMMU to master */ 120 struct rk_iommu *iommu; 121}; 122 123static struct device *dma_dev; 124static const struct rk_iommu_ops *rk_ops; 125static struct iommu_domain rk_identity_domain; 126 127static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, 128 unsigned int count) 129{ 130 size_t size = count * sizeof(u32); /* count of u32 entry */ 131 132 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE); 133} 134 135static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) 136{ 137 return container_of(dom, struct rk_iommu_domain, domain); 138} 139 140/* 141 * The Rockchip rk3288 iommu uses a 2-level page table. 142 * The first level is the "Directory Table" (DT). 143 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing 144 * to a "Page Table". 145 * The second level is the 1024 Page Tables (PT). 146 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to 147 * a 4 KB page of physical memory. 148 * 149 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). 150 * Each iommu device has a MMU_DTE_ADDR register that contains the physical 151 * address of the start of the DT page. 152 * 153 * The structure of the page table is as follows: 154 * 155 * DT 156 * MMU_DTE_ADDR -> +-----+ 157 * | | 158 * +-----+ PT 159 * | DTE | -> +-----+ 160 * +-----+ | | Memory 161 * | | +-----+ Page 162 * | | | PTE | -> +-----+ 163 * +-----+ +-----+ | | 164 * | | | | 165 * | | | | 166 * +-----+ | | 167 * | | 168 * | | 169 * +-----+ 170 */ 171 172/* 173 * Each DTE has a PT address and a valid bit: 174 * +---------------------+-----------+-+ 175 * | PT address | Reserved |V| 176 * +---------------------+-----------+-+ 177 * 31:12 - PT address (PTs always starts on a 4 KB boundary) 178 * 11: 1 - Reserved 179 * 0 - 1 if PT @ PT address is valid 180 */ 181#define RK_DTE_PT_ADDRESS_MASK 0xfffff000 182#define RK_DTE_PT_VALID BIT(0) 183 184static inline phys_addr_t rk_dte_pt_address(u32 dte) 185{ 186 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; 187} 188 189/* 190 * In v2: 191 * 31:12 - PT address bit 31:0 192 * 11: 8 - PT address bit 35:32 193 * 7: 4 - PT address bit 39:36 194 * 3: 1 - Reserved 195 * 0 - 1 if PT @ PT address is valid 196 */ 197#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4) 198#define DTE_HI_MASK1 GENMASK(11, 8) 199#define DTE_HI_MASK2 GENMASK(7, 4) 200#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ 201#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ 202#define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32) 203#define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36) 204 205static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) 206{ 207 u64 dte_v2 = dte; 208 209 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) | 210 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) | 211 (dte_v2 & RK_DTE_PT_ADDRESS_MASK); 212 213 return (phys_addr_t)dte_v2; 214} 215 216static inline bool rk_dte_is_pt_valid(u32 dte) 217{ 218 return dte & RK_DTE_PT_VALID; 219} 220 221static inline u32 rk_mk_dte(dma_addr_t pt_dma) 222{ 223 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; 224} 225 226static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma) 227{ 228 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) | 229 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) | 230 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2; 231 232 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID; 233} 234 235/* 236 * Each PTE has a Page address, some flags and a valid bit: 237 * +---------------------+---+-------+-+ 238 * | Page address |Rsv| Flags |V| 239 * +---------------------+---+-------+-+ 240 * 31:12 - Page address (Pages always start on a 4 KB boundary) 241 * 11: 9 - Reserved 242 * 8: 1 - Flags 243 * 8 - Read allocate - allocate cache space on read misses 244 * 7 - Read cache - enable cache & prefetch of data 245 * 6 - Write buffer - enable delaying writes on their way to memory 246 * 5 - Write allocate - allocate cache space on write misses 247 * 4 - Write cache - different writes can be merged together 248 * 3 - Override cache attributes 249 * if 1, bits 4-8 control cache attributes 250 * if 0, the system bus defaults are used 251 * 2 - Writable 252 * 1 - Readable 253 * 0 - 1 if Page @ Page address is valid 254 */ 255#define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 256#define RK_PTE_PAGE_FLAGS_MASK 0x000001fe 257#define RK_PTE_PAGE_WRITABLE BIT(2) 258#define RK_PTE_PAGE_READABLE BIT(1) 259#define RK_PTE_PAGE_VALID BIT(0) 260 261static inline bool rk_pte_is_page_valid(u32 pte) 262{ 263 return pte & RK_PTE_PAGE_VALID; 264} 265 266/* TODO: set cache flags per prot IOMMU_CACHE */ 267static u32 rk_mk_pte(phys_addr_t page, int prot) 268{ 269 u32 flags = 0; 270 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 271 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 272 page &= RK_PTE_PAGE_ADDRESS_MASK; 273 return page | flags | RK_PTE_PAGE_VALID; 274} 275 276/* 277 * In v2: 278 * 31:12 - Page address bit 31:0 279 * 11: 8 - Page address bit 35:32 280 * 7: 4 - Page address bit 39:36 281 * 3 - Security 282 * 2 - Writable 283 * 1 - Readable 284 * 0 - 1 if Page @ Page address is valid 285 */ 286 287static u32 rk_mk_pte_v2(phys_addr_t page, int prot) 288{ 289 u32 flags = 0; 290 291 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 292 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 293 294 return rk_mk_dte_v2(page) | flags; 295} 296 297static u32 rk_mk_pte_invalid(u32 pte) 298{ 299 return pte & ~RK_PTE_PAGE_VALID; 300} 301 302/* 303 * rk3288 iova (IOMMU Virtual Address) format 304 * 31 22.21 12.11 0 305 * +-----------+-----------+-------------+ 306 * | DTE index | PTE index | Page offset | 307 * +-----------+-----------+-------------+ 308 * 31:22 - DTE index - index of DTE in DT 309 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address 310 * 11: 0 - Page offset - offset into page @ PTE.page_address 311 */ 312#define RK_IOVA_DTE_MASK 0xffc00000 313#define RK_IOVA_DTE_SHIFT 22 314#define RK_IOVA_PTE_MASK 0x003ff000 315#define RK_IOVA_PTE_SHIFT 12 316#define RK_IOVA_PAGE_MASK 0x00000fff 317#define RK_IOVA_PAGE_SHIFT 0 318 319static u32 rk_iova_dte_index(dma_addr_t iova) 320{ 321 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; 322} 323 324static u32 rk_iova_pte_index(dma_addr_t iova) 325{ 326 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; 327} 328 329static u32 rk_iova_page_offset(dma_addr_t iova) 330{ 331 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; 332} 333 334static u32 rk_iommu_read(void __iomem *base, u32 offset) 335{ 336 return readl(base + offset); 337} 338 339static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) 340{ 341 writel(value, base + offset); 342} 343 344static void rk_iommu_command(struct rk_iommu *iommu, u32 command) 345{ 346 int i; 347 348 for (i = 0; i < iommu->num_mmu; i++) 349 writel(command, iommu->bases[i] + RK_MMU_COMMAND); 350} 351 352static void rk_iommu_base_command(void __iomem *base, u32 command) 353{ 354 writel(command, base + RK_MMU_COMMAND); 355} 356static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, 357 size_t size) 358{ 359 int i; 360 dma_addr_t iova_end = iova_start + size; 361 /* 362 * TODO(djkurtz): Figure out when it is more efficient to shootdown the 363 * entire iotlb rather than iterate over individual iovas. 364 */ 365 for (i = 0; i < iommu->num_mmu; i++) { 366 dma_addr_t iova; 367 368 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) 369 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); 370 } 371} 372 373static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) 374{ 375 bool active = true; 376 int i; 377 378 for (i = 0; i < iommu->num_mmu; i++) 379 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 380 RK_MMU_STATUS_STALL_ACTIVE); 381 382 return active; 383} 384 385static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) 386{ 387 bool enable = true; 388 int i; 389 390 for (i = 0; i < iommu->num_mmu; i++) 391 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 392 RK_MMU_STATUS_PAGING_ENABLED); 393 394 return enable; 395} 396 397static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) 398{ 399 bool done = true; 400 int i; 401 402 for (i = 0; i < iommu->num_mmu; i++) 403 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; 404 405 return done; 406} 407 408static int rk_iommu_enable_stall(struct rk_iommu *iommu) 409{ 410 int ret, i; 411 bool val; 412 413 if (rk_iommu_is_stall_active(iommu)) 414 return 0; 415 416 /* Stall can only be enabled if paging is enabled */ 417 if (!rk_iommu_is_paging_enabled(iommu)) 418 return 0; 419 420 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); 421 422 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 423 val, RK_MMU_POLL_PERIOD_US, 424 RK_MMU_POLL_TIMEOUT_US); 425 if (ret) 426 for (i = 0; i < iommu->num_mmu; i++) 427 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", 428 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 429 430 return ret; 431} 432 433static int rk_iommu_disable_stall(struct rk_iommu *iommu) 434{ 435 int ret, i; 436 bool val; 437 438 if (!rk_iommu_is_stall_active(iommu)) 439 return 0; 440 441 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); 442 443 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 444 !val, RK_MMU_POLL_PERIOD_US, 445 RK_MMU_POLL_TIMEOUT_US); 446 if (ret) 447 for (i = 0; i < iommu->num_mmu; i++) 448 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", 449 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 450 451 return ret; 452} 453 454static int rk_iommu_enable_paging(struct rk_iommu *iommu) 455{ 456 int ret, i; 457 bool val; 458 459 if (rk_iommu_is_paging_enabled(iommu)) 460 return 0; 461 462 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); 463 464 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 465 val, RK_MMU_POLL_PERIOD_US, 466 RK_MMU_POLL_TIMEOUT_US); 467 if (ret) 468 for (i = 0; i < iommu->num_mmu; i++) 469 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", 470 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 471 472 return ret; 473} 474 475static int rk_iommu_disable_paging(struct rk_iommu *iommu) 476{ 477 int ret, i; 478 bool val; 479 480 if (!rk_iommu_is_paging_enabled(iommu)) 481 return 0; 482 483 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); 484 485 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 486 !val, RK_MMU_POLL_PERIOD_US, 487 RK_MMU_POLL_TIMEOUT_US); 488 if (ret) 489 for (i = 0; i < iommu->num_mmu; i++) 490 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", 491 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 492 493 return ret; 494} 495 496static int rk_iommu_force_reset(struct rk_iommu *iommu) 497{ 498 int ret, i; 499 u32 dte_addr; 500 bool val; 501 502 if (iommu->reset_disabled) 503 return 0; 504 505 /* 506 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY 507 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back. 508 */ 509 for (i = 0; i < iommu->num_mmu; i++) { 510 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); 511 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 512 513 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { 514 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); 515 return -EFAULT; 516 } 517 } 518 519 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); 520 521 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, 522 val, RK_MMU_FORCE_RESET_TIMEOUT_US, 523 RK_MMU_POLL_TIMEOUT_US); 524 if (ret) { 525 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); 526 return ret; 527 } 528 529 return 0; 530} 531 532static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) 533{ 534 void __iomem *base = iommu->bases[index]; 535 u32 dte_index, pte_index, page_offset; 536 u32 mmu_dte_addr; 537 phys_addr_t mmu_dte_addr_phys, dte_addr_phys; 538 u32 *dte_addr; 539 u32 dte; 540 phys_addr_t pte_addr_phys = 0; 541 u32 *pte_addr = NULL; 542 u32 pte = 0; 543 phys_addr_t page_addr_phys = 0; 544 u32 page_flags = 0; 545 546 dte_index = rk_iova_dte_index(iova); 547 pte_index = rk_iova_pte_index(iova); 548 page_offset = rk_iova_page_offset(iova); 549 550 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); 551 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr); 552 553 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); 554 dte_addr = phys_to_virt(dte_addr_phys); 555 dte = *dte_addr; 556 557 if (!rk_dte_is_pt_valid(dte)) 558 goto print_it; 559 560 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); 561 pte_addr = phys_to_virt(pte_addr_phys); 562 pte = *pte_addr; 563 564 if (!rk_pte_is_page_valid(pte)) 565 goto print_it; 566 567 page_addr_phys = rk_ops->pt_address(pte) + page_offset; 568 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; 569 570print_it: 571 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", 572 &iova, dte_index, pte_index, page_offset); 573 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", 574 &mmu_dte_addr_phys, &dte_addr_phys, dte, 575 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, 576 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); 577} 578 579static irqreturn_t rk_iommu_irq(int irq, void *dev_id) 580{ 581 struct rk_iommu *iommu = dev_id; 582 u32 status; 583 u32 int_status; 584 dma_addr_t iova; 585 irqreturn_t ret = IRQ_NONE; 586 int i, err; 587 588 err = pm_runtime_get_if_in_use(iommu->dev); 589 if (!err || WARN_ON_ONCE(err < 0)) 590 return ret; 591 592 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 593 goto out; 594 595 for (i = 0; i < iommu->num_mmu; i++) { 596 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); 597 if (int_status == 0) 598 continue; 599 600 ret = IRQ_HANDLED; 601 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); 602 603 if (int_status & RK_MMU_IRQ_PAGE_FAULT) { 604 int flags; 605 606 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); 607 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? 608 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 609 610 dev_err(iommu->dev, "Page fault at %pad of type %s\n", 611 &iova, 612 (flags == IOMMU_FAULT_WRITE) ? "write" : "read"); 613 614 log_iova(iommu, i, iova); 615 616 /* 617 * Report page fault to any installed handlers. 618 * Ignore the return code, though, since we always zap cache 619 * and clear the page fault anyway. 620 */ 621 if (iommu->domain != &rk_identity_domain) 622 report_iommu_fault(iommu->domain, iommu->dev, iova, 623 flags); 624 else 625 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); 626 627 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 628 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); 629 } 630 631 if (int_status & RK_MMU_IRQ_BUS_ERROR) 632 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); 633 634 if (int_status & ~RK_MMU_IRQ_MASK) 635 dev_err(iommu->dev, "unexpected int_status: %#08x\n", 636 int_status); 637 638 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); 639 } 640 641 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 642 643out: 644 pm_runtime_put(iommu->dev); 645 return ret; 646} 647 648static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, 649 dma_addr_t iova) 650{ 651 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 652 unsigned long flags; 653 phys_addr_t pt_phys, phys = 0; 654 u32 dte, pte; 655 u32 *page_table; 656 657 spin_lock_irqsave(&rk_domain->dt_lock, flags); 658 659 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 660 if (!rk_dte_is_pt_valid(dte)) 661 goto out; 662 663 pt_phys = rk_ops->pt_address(dte); 664 page_table = (u32 *)phys_to_virt(pt_phys); 665 pte = page_table[rk_iova_pte_index(iova)]; 666 if (!rk_pte_is_page_valid(pte)) 667 goto out; 668 669 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); 670out: 671 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 672 673 return phys; 674} 675 676static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, 677 dma_addr_t iova, size_t size) 678{ 679 struct list_head *pos; 680 unsigned long flags; 681 682 /* shootdown these iova from all iommus using this domain */ 683 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 684 list_for_each(pos, &rk_domain->iommus) { 685 struct rk_iommu *iommu; 686 int ret; 687 688 iommu = list_entry(pos, struct rk_iommu, node); 689 690 /* Only zap TLBs of IOMMUs that are powered on. */ 691 ret = pm_runtime_get_if_in_use(iommu->dev); 692 if (WARN_ON_ONCE(ret < 0)) 693 continue; 694 if (ret) { 695 WARN_ON(clk_bulk_enable(iommu->num_clocks, 696 iommu->clocks)); 697 rk_iommu_zap_lines(iommu, iova, size); 698 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 699 pm_runtime_put(iommu->dev); 700 } 701 } 702 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 703} 704 705static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, 706 dma_addr_t iova, size_t size) 707{ 708 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); 709 if (size > SPAGE_SIZE) 710 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, 711 SPAGE_SIZE); 712} 713 714static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, 715 dma_addr_t iova) 716{ 717 u32 *page_table, *dte_addr; 718 u32 dte_index, dte; 719 phys_addr_t pt_phys; 720 dma_addr_t pt_dma; 721 722 assert_spin_locked(&rk_domain->dt_lock); 723 724 dte_index = rk_iova_dte_index(iova); 725 dte_addr = &rk_domain->dt[dte_index]; 726 dte = *dte_addr; 727 if (rk_dte_is_pt_valid(dte)) 728 goto done; 729 730 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | rk_ops->gfp_flags); 731 if (!page_table) 732 return ERR_PTR(-ENOMEM); 733 734 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); 735 if (dma_mapping_error(dma_dev, pt_dma)) { 736 dev_err(dma_dev, "DMA mapping error while allocating page table\n"); 737 free_page((unsigned long)page_table); 738 return ERR_PTR(-ENOMEM); 739 } 740 741 dte = rk_ops->mk_dtentries(pt_dma); 742 *dte_addr = dte; 743 744 rk_table_flush(rk_domain, 745 rk_domain->dt_dma + dte_index * sizeof(u32), 1); 746done: 747 pt_phys = rk_ops->pt_address(dte); 748 return (u32 *)phys_to_virt(pt_phys); 749} 750 751static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, 752 u32 *pte_addr, dma_addr_t pte_dma, 753 size_t size) 754{ 755 unsigned int pte_count; 756 unsigned int pte_total = size / SPAGE_SIZE; 757 758 assert_spin_locked(&rk_domain->dt_lock); 759 760 for (pte_count = 0; pte_count < pte_total; pte_count++) { 761 u32 pte = pte_addr[pte_count]; 762 if (!rk_pte_is_page_valid(pte)) 763 break; 764 765 pte_addr[pte_count] = rk_mk_pte_invalid(pte); 766 } 767 768 rk_table_flush(rk_domain, pte_dma, pte_count); 769 770 return pte_count * SPAGE_SIZE; 771} 772 773static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, 774 dma_addr_t pte_dma, dma_addr_t iova, 775 phys_addr_t paddr, size_t size, int prot) 776{ 777 unsigned int pte_count; 778 unsigned int pte_total = size / SPAGE_SIZE; 779 phys_addr_t page_phys; 780 781 assert_spin_locked(&rk_domain->dt_lock); 782 783 for (pte_count = 0; pte_count < pte_total; pte_count++) { 784 u32 pte = pte_addr[pte_count]; 785 786 if (rk_pte_is_page_valid(pte)) 787 goto unwind; 788 789 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); 790 791 paddr += SPAGE_SIZE; 792 } 793 794 rk_table_flush(rk_domain, pte_dma, pte_total); 795 796 /* 797 * Zap the first and last iova to evict from iotlb any previously 798 * mapped cachelines holding stale values for its dte and pte. 799 * We only zap the first and last iova, since only they could have 800 * dte or pte shared with an existing mapping. 801 */ 802 rk_iommu_zap_iova_first_last(rk_domain, iova, size); 803 804 return 0; 805unwind: 806 /* Unmap the range of iovas that we just mapped */ 807 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, 808 pte_count * SPAGE_SIZE); 809 810 iova += pte_count * SPAGE_SIZE; 811 page_phys = rk_ops->pt_address(pte_addr[pte_count]); 812 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", 813 &iova, &page_phys, &paddr, prot); 814 815 return -EADDRINUSE; 816} 817 818static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, 819 phys_addr_t paddr, size_t size, size_t count, 820 int prot, gfp_t gfp, size_t *mapped) 821{ 822 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 823 unsigned long flags; 824 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 825 u32 *page_table, *pte_addr; 826 u32 dte_index, pte_index; 827 int ret; 828 829 spin_lock_irqsave(&rk_domain->dt_lock, flags); 830 831 /* 832 * pgsize_bitmap specifies iova sizes that fit in one page table 833 * (1024 4-KiB pages = 4 MiB). 834 * So, size will always be 4096 <= size <= 4194304. 835 * Since iommu_map() guarantees that both iova and size will be 836 * aligned, we will always only be mapping from a single dte here. 837 */ 838 page_table = rk_dte_get_page_table(rk_domain, iova); 839 if (IS_ERR(page_table)) { 840 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 841 return PTR_ERR(page_table); 842 } 843 844 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; 845 pte_index = rk_iova_pte_index(iova); 846 pte_addr = &page_table[pte_index]; 847 848 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); 849 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, 850 paddr, size, prot); 851 852 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 853 if (!ret) 854 *mapped = size; 855 856 return ret; 857} 858 859static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, 860 size_t size, size_t count, struct iommu_iotlb_gather *gather) 861{ 862 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 863 unsigned long flags; 864 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 865 phys_addr_t pt_phys; 866 u32 dte; 867 u32 *pte_addr; 868 size_t unmap_size; 869 870 spin_lock_irqsave(&rk_domain->dt_lock, flags); 871 872 /* 873 * pgsize_bitmap specifies iova sizes that fit in one page table 874 * (1024 4-KiB pages = 4 MiB). 875 * So, size will always be 4096 <= size <= 4194304. 876 * Since iommu_unmap() guarantees that both iova and size will be 877 * aligned, we will always only be unmapping from a single dte here. 878 */ 879 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 880 /* Just return 0 if iova is unmapped */ 881 if (!rk_dte_is_pt_valid(dte)) { 882 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 883 return 0; 884 } 885 886 pt_phys = rk_ops->pt_address(dte); 887 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); 888 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); 889 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); 890 891 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 892 893 /* Shootdown iotlb entries for iova range that was just unmapped */ 894 rk_iommu_zap_iova(rk_domain, iova, unmap_size); 895 896 return unmap_size; 897} 898 899static struct rk_iommu *rk_iommu_from_dev(struct device *dev) 900{ 901 struct rk_iommudata *data = dev_iommu_priv_get(dev); 902 903 return data ? data->iommu : NULL; 904} 905 906/* Must be called with iommu powered on and attached */ 907static void rk_iommu_disable(struct rk_iommu *iommu) 908{ 909 int i; 910 911 /* Ignore error while disabling, just keep going */ 912 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); 913 rk_iommu_enable_stall(iommu); 914 rk_iommu_disable_paging(iommu); 915 for (i = 0; i < iommu->num_mmu; i++) { 916 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); 917 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); 918 } 919 rk_iommu_disable_stall(iommu); 920 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 921} 922 923/* Must be called with iommu powered on and attached */ 924static int rk_iommu_enable(struct rk_iommu *iommu) 925{ 926 struct iommu_domain *domain = iommu->domain; 927 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 928 int ret, i; 929 930 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); 931 if (ret) 932 return ret; 933 934 ret = rk_iommu_enable_stall(iommu); 935 if (ret) 936 goto out_disable_clocks; 937 938 ret = rk_iommu_force_reset(iommu); 939 if (ret) 940 goto out_disable_stall; 941 942 for (i = 0; i < iommu->num_mmu; i++) { 943 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 944 rk_ops->mk_dtentries(rk_domain->dt_dma)); 945 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 946 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 947 } 948 949 ret = rk_iommu_enable_paging(iommu); 950 951out_disable_stall: 952 rk_iommu_disable_stall(iommu); 953out_disable_clocks: 954 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 955 return ret; 956} 957 958static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, 959 struct device *dev) 960{ 961 struct rk_iommu *iommu; 962 struct rk_iommu_domain *rk_domain; 963 unsigned long flags; 964 int ret; 965 966 /* Allow 'virtual devices' (eg drm) to detach from domain */ 967 iommu = rk_iommu_from_dev(dev); 968 if (!iommu) 969 return -ENODEV; 970 971 rk_domain = to_rk_domain(iommu->domain); 972 973 dev_dbg(dev, "Detaching from iommu domain\n"); 974 975 if (iommu->domain == identity_domain) 976 return 0; 977 978 iommu->domain = identity_domain; 979 980 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 981 list_del_init(&iommu->node); 982 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 983 984 ret = pm_runtime_get_if_in_use(iommu->dev); 985 WARN_ON_ONCE(ret < 0); 986 if (ret > 0) { 987 rk_iommu_disable(iommu); 988 pm_runtime_put(iommu->dev); 989 } 990 991 return 0; 992} 993 994static struct iommu_domain_ops rk_identity_ops = { 995 .attach_dev = rk_iommu_identity_attach, 996}; 997 998static struct iommu_domain rk_identity_domain = { 999 .type = IOMMU_DOMAIN_IDENTITY, 1000 .ops = &rk_identity_ops, 1001}; 1002 1003static int rk_iommu_attach_device(struct iommu_domain *domain, 1004 struct device *dev) 1005{ 1006 struct rk_iommu *iommu; 1007 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1008 unsigned long flags; 1009 int ret; 1010 1011 /* 1012 * Allow 'virtual devices' (e.g., drm) to attach to domain. 1013 * Such a device does not belong to an iommu group. 1014 */ 1015 iommu = rk_iommu_from_dev(dev); 1016 if (!iommu) 1017 return 0; 1018 1019 dev_dbg(dev, "Attaching to iommu domain\n"); 1020 1021 /* iommu already attached */ 1022 if (iommu->domain == domain) 1023 return 0; 1024 1025 ret = rk_iommu_identity_attach(&rk_identity_domain, dev); 1026 if (ret) 1027 return ret; 1028 1029 iommu->domain = domain; 1030 1031 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1032 list_add_tail(&iommu->node, &rk_domain->iommus); 1033 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1034 1035 ret = pm_runtime_get_if_in_use(iommu->dev); 1036 if (!ret || WARN_ON_ONCE(ret < 0)) 1037 return 0; 1038 1039 ret = rk_iommu_enable(iommu); 1040 if (ret) 1041 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev)); 1042 1043 pm_runtime_put(iommu->dev); 1044 1045 return ret; 1046} 1047 1048static struct iommu_domain *rk_iommu_domain_alloc_paging(struct device *dev) 1049{ 1050 struct rk_iommu_domain *rk_domain; 1051 1052 if (!dma_dev) 1053 return NULL; 1054 1055 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL); 1056 if (!rk_domain) 1057 return NULL; 1058 1059 /* 1060 * rk32xx iommus use a 2 level pagetable. 1061 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. 1062 * Allocate one 4 KiB page for each table. 1063 */ 1064 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | rk_ops->gfp_flags); 1065 if (!rk_domain->dt) 1066 goto err_free_domain; 1067 1068 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt, 1069 SPAGE_SIZE, DMA_TO_DEVICE); 1070 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) { 1071 dev_err(dma_dev, "DMA map error for DT\n"); 1072 goto err_free_dt; 1073 } 1074 1075 spin_lock_init(&rk_domain->iommus_lock); 1076 spin_lock_init(&rk_domain->dt_lock); 1077 INIT_LIST_HEAD(&rk_domain->iommus); 1078 1079 rk_domain->domain.geometry.aperture_start = 0; 1080 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); 1081 rk_domain->domain.geometry.force_aperture = true; 1082 1083 return &rk_domain->domain; 1084 1085err_free_dt: 1086 free_page((unsigned long)rk_domain->dt); 1087err_free_domain: 1088 kfree(rk_domain); 1089 1090 return NULL; 1091} 1092 1093static void rk_iommu_domain_free(struct iommu_domain *domain) 1094{ 1095 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1096 int i; 1097 1098 WARN_ON(!list_empty(&rk_domain->iommus)); 1099 1100 for (i = 0; i < NUM_DT_ENTRIES; i++) { 1101 u32 dte = rk_domain->dt[i]; 1102 if (rk_dte_is_pt_valid(dte)) { 1103 phys_addr_t pt_phys = rk_ops->pt_address(dte); 1104 u32 *page_table = phys_to_virt(pt_phys); 1105 dma_unmap_single(dma_dev, pt_phys, 1106 SPAGE_SIZE, DMA_TO_DEVICE); 1107 free_page((unsigned long)page_table); 1108 } 1109 } 1110 1111 dma_unmap_single(dma_dev, rk_domain->dt_dma, 1112 SPAGE_SIZE, DMA_TO_DEVICE); 1113 free_page((unsigned long)rk_domain->dt); 1114 1115 kfree(rk_domain); 1116} 1117 1118static struct iommu_device *rk_iommu_probe_device(struct device *dev) 1119{ 1120 struct rk_iommudata *data; 1121 struct rk_iommu *iommu; 1122 1123 data = dev_iommu_priv_get(dev); 1124 if (!data) 1125 return ERR_PTR(-ENODEV); 1126 1127 iommu = rk_iommu_from_dev(dev); 1128 1129 data->link = device_link_add(dev, iommu->dev, 1130 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1131 1132 return &iommu->iommu; 1133} 1134 1135static void rk_iommu_release_device(struct device *dev) 1136{ 1137 struct rk_iommudata *data = dev_iommu_priv_get(dev); 1138 1139 device_link_del(data->link); 1140} 1141 1142static int rk_iommu_of_xlate(struct device *dev, 1143 const struct of_phandle_args *args) 1144{ 1145 struct platform_device *iommu_dev; 1146 struct rk_iommudata *data; 1147 1148 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); 1149 if (!data) 1150 return -ENOMEM; 1151 1152 iommu_dev = of_find_device_by_node(args->np); 1153 1154 data->iommu = platform_get_drvdata(iommu_dev); 1155 data->iommu->domain = &rk_identity_domain; 1156 dev_iommu_priv_set(dev, data); 1157 1158 platform_device_put(iommu_dev); 1159 1160 return 0; 1161} 1162 1163static const struct iommu_ops rk_iommu_ops = { 1164 .identity_domain = &rk_identity_domain, 1165 .domain_alloc_paging = rk_iommu_domain_alloc_paging, 1166 .probe_device = rk_iommu_probe_device, 1167 .release_device = rk_iommu_release_device, 1168 .device_group = generic_single_device_group, 1169 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, 1170 .of_xlate = rk_iommu_of_xlate, 1171 .default_domain_ops = &(const struct iommu_domain_ops) { 1172 .attach_dev = rk_iommu_attach_device, 1173 .map_pages = rk_iommu_map, 1174 .unmap_pages = rk_iommu_unmap, 1175 .iova_to_phys = rk_iommu_iova_to_phys, 1176 .free = rk_iommu_domain_free, 1177 } 1178}; 1179 1180static int rk_iommu_probe(struct platform_device *pdev) 1181{ 1182 struct device *dev = &pdev->dev; 1183 struct rk_iommu *iommu; 1184 struct resource *res; 1185 const struct rk_iommu_ops *ops; 1186 int num_res = pdev->num_resources; 1187 int err, i; 1188 1189 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 1190 if (!iommu) 1191 return -ENOMEM; 1192 1193 platform_set_drvdata(pdev, iommu); 1194 iommu->dev = dev; 1195 iommu->num_mmu = 0; 1196 1197 ops = of_device_get_match_data(dev); 1198 if (!rk_ops) 1199 rk_ops = ops; 1200 1201 /* 1202 * That should not happen unless different versions of the 1203 * hardware block are embedded the same SoC 1204 */ 1205 if (WARN_ON(rk_ops != ops)) 1206 return -EINVAL; 1207 1208 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), 1209 GFP_KERNEL); 1210 if (!iommu->bases) 1211 return -ENOMEM; 1212 1213 for (i = 0; i < num_res; i++) { 1214 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1215 if (!res) 1216 continue; 1217 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); 1218 if (IS_ERR(iommu->bases[i])) 1219 continue; 1220 iommu->num_mmu++; 1221 } 1222 if (iommu->num_mmu == 0) 1223 return PTR_ERR(iommu->bases[0]); 1224 1225 iommu->num_irq = platform_irq_count(pdev); 1226 if (iommu->num_irq < 0) 1227 return iommu->num_irq; 1228 1229 iommu->reset_disabled = device_property_read_bool(dev, 1230 "rockchip,disable-mmu-reset"); 1231 1232 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); 1233 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, 1234 sizeof(*iommu->clocks), GFP_KERNEL); 1235 if (!iommu->clocks) 1236 return -ENOMEM; 1237 1238 for (i = 0; i < iommu->num_clocks; ++i) 1239 iommu->clocks[i].id = rk_iommu_clocks[i]; 1240 1241 /* 1242 * iommu clocks should be present for all new devices and devicetrees 1243 * but there are older devicetrees without clocks out in the wild. 1244 * So clocks as optional for the time being. 1245 */ 1246 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); 1247 if (err == -ENOENT) 1248 iommu->num_clocks = 0; 1249 else if (err) 1250 return err; 1251 1252 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); 1253 if (err) 1254 return err; 1255 1256 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); 1257 if (err) 1258 goto err_unprepare_clocks; 1259 1260 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); 1261 if (err) 1262 goto err_remove_sysfs; 1263 1264 /* 1265 * Use the first registered IOMMU device for domain to use with DMA 1266 * API, since a domain might not physically correspond to a single 1267 * IOMMU device.. 1268 */ 1269 if (!dma_dev) 1270 dma_dev = &pdev->dev; 1271 1272 pm_runtime_enable(dev); 1273 1274 for (i = 0; i < iommu->num_irq; i++) { 1275 int irq = platform_get_irq(pdev, i); 1276 1277 if (irq < 0) { 1278 err = irq; 1279 goto err_pm_disable; 1280 } 1281 1282 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1283 IRQF_SHARED, dev_name(dev), iommu); 1284 if (err) 1285 goto err_pm_disable; 1286 } 1287 1288 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); 1289 1290 return 0; 1291err_pm_disable: 1292 pm_runtime_disable(dev); 1293err_remove_sysfs: 1294 iommu_device_sysfs_remove(&iommu->iommu); 1295err_unprepare_clocks: 1296 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); 1297 return err; 1298} 1299 1300static void rk_iommu_shutdown(struct platform_device *pdev) 1301{ 1302 struct rk_iommu *iommu = platform_get_drvdata(pdev); 1303 int i; 1304 1305 for (i = 0; i < iommu->num_irq; i++) { 1306 int irq = platform_get_irq(pdev, i); 1307 1308 devm_free_irq(iommu->dev, irq, iommu); 1309 } 1310 1311 pm_runtime_force_suspend(&pdev->dev); 1312} 1313 1314static int __maybe_unused rk_iommu_suspend(struct device *dev) 1315{ 1316 struct rk_iommu *iommu = dev_get_drvdata(dev); 1317 1318 if (iommu->domain == &rk_identity_domain) 1319 return 0; 1320 1321 rk_iommu_disable(iommu); 1322 return 0; 1323} 1324 1325static int __maybe_unused rk_iommu_resume(struct device *dev) 1326{ 1327 struct rk_iommu *iommu = dev_get_drvdata(dev); 1328 1329 if (iommu->domain == &rk_identity_domain) 1330 return 0; 1331 1332 return rk_iommu_enable(iommu); 1333} 1334 1335static const struct dev_pm_ops rk_iommu_pm_ops = { 1336 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) 1337 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1338 pm_runtime_force_resume) 1339}; 1340 1341static struct rk_iommu_ops iommu_data_ops_v1 = { 1342 .pt_address = &rk_dte_pt_address, 1343 .mk_dtentries = &rk_mk_dte, 1344 .mk_ptentries = &rk_mk_pte, 1345 .dma_bit_mask = DMA_BIT_MASK(32), 1346 .gfp_flags = GFP_DMA32, 1347}; 1348 1349static struct rk_iommu_ops iommu_data_ops_v2 = { 1350 .pt_address = &rk_dte_pt_address_v2, 1351 .mk_dtentries = &rk_mk_dte_v2, 1352 .mk_ptentries = &rk_mk_pte_v2, 1353 .dma_bit_mask = DMA_BIT_MASK(40), 1354 .gfp_flags = 0, 1355}; 1356 1357static const struct of_device_id rk_iommu_dt_ids[] = { 1358 { .compatible = "rockchip,iommu", 1359 .data = &iommu_data_ops_v1, 1360 }, 1361 { .compatible = "rockchip,rk3568-iommu", 1362 .data = &iommu_data_ops_v2, 1363 }, 1364 { /* sentinel */ } 1365}; 1366 1367static struct platform_driver rk_iommu_driver = { 1368 .probe = rk_iommu_probe, 1369 .shutdown = rk_iommu_shutdown, 1370 .driver = { 1371 .name = "rk_iommu", 1372 .of_match_table = rk_iommu_dt_ids, 1373 .pm = &rk_iommu_pm_ops, 1374 .suppress_bind_attrs = true, 1375 }, 1376}; 1377builtin_platform_driver(rk_iommu_driver); 1378