Searched refs:base_reg (Results 1 - 25 of 56) sorted by relevance

123

/linux-master/arch/sparc/include/asm/
H A Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
42 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
44 #define LOAD_PT_GLOBALS(base_reg) \
45 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
48 ldd [%base_reg
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/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c394 u64 base_reg; local
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
413 WREG32(base_reg + 0xE80, 0x80004);
414 WREG32(base_reg + 0xD64, 7);
415 WREG32(base_reg + 0xD60, 0);
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
417 WREG32(base_reg + 0xD60, 1);
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
419 WREG32(base_reg
472 u64 base_reg; local
701 u64 base_reg; local
721 u64 base_reg; local
782 u64 base_reg; local
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/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c232 u64 base_reg; local
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
251 WREG32(base_reg + 0xE80, 0x80004);
252 WREG32(base_reg + 0xD64, 7);
253 WREG32(base_reg + 0xD60, 0);
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
256 WREG32(base_reg + 0xD60, 1);
257 WREG32(base_reg
305 u64 base_reg; local
487 u64 base_reg; local
507 u64 base_reg; local
578 u64 base_reg; local
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/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-blkctl.c26 void __iomem *base_reg; member in struct:dcss_blkctl
32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
35 blkctl->base_reg + DCSS_BLKCTL_CONTROL0);
38 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL);
49 blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K);
50 if (!blkctl->base_reg) {
H A Ddcss-dtg.c80 void __iomem *base_reg; member in struct:dcss_dtg
101 dcss_writel(val, dtg->base_reg + ofs);
112 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
134 dtg->base_reg + DCSS_DTG_INT_MASK);
163 dtg->base_reg = devm_ioremap(dtg->dev, dtg_base, SZ_4K);
164 if (!dtg->base_reg) {
314 dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS);
347 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
349 dtg->base_reg
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H A Ddcss-ss.c64 void __iomem *base_reg; member in struct:dcss_ss
76 dcss_writel(val, ss->base_reg + ofs);
94 ss->base_reg = devm_ioremap(ss->dev, ss_base, SZ_4K);
95 if (!ss->base_reg) {
109 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL);
172 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL);
/linux-master/drivers/base/regmap/
H A Dregcache-rbtree.c27 unsigned int base_reg; member in struct:regcache_rbtree_node
44 *base = rbnode->base_reg;
45 *top = rbnode->base_reg + ((rbnode->blklen - 1) * map->reg_stride);
68 unsigned int base_reg, top_reg; local
72 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
74 if (reg >= base_reg && reg <= top_reg)
81 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
83 if (reg >= base_reg && reg <= top_reg) {
88 } else if (reg < base_reg) {
102 unsigned int base_reg; local
262 regcache_rbtree_insert_to_block(struct regmap *map, struct regcache_rbtree_node *rbnode, unsigned int base_reg, unsigned int top_reg, unsigned int reg, unsigned int value) argument
387 unsigned int base_reg, top_reg; local
471 unsigned int base_reg, top_reg; local
516 unsigned int base_reg, top_reg; local
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/linux-master/drivers/crypto/intel/keembay/
H A Docs-aes.c206 iowrite32(0x7FF, aes_dev->base_reg + AES_BYTE_ORDER_CFG_OFFSET);
212 iowrite32(AES_ACTIVE_TRIGGER, aes_dev->base_reg + AES_ACTIVE_OFFSET);
219 aes_dev->base_reg + AES_ACTIVE_OFFSET);
234 aes_dev->base_reg + AES_ACTIVE_OFFSET);
243 aes_active_reg = ioread32(aes_dev->base_reg +
254 reg = ioread32(aes_dev->base_reg + AES_A_DMA_STATUS_OFFSET);
268 aes_dev->base_reg + AES_ACTIVE_OFFSET);
274 iowrite32(0, aes_dev->base_reg + AES_A_DMA_SRC_SIZE_OFFSET);
275 iowrite32(0, aes_dev->base_reg + AES_A_DMA_DST_SIZE_OFFSET);
282 aes_dev->base_reg
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H A Dkeembay-ocs-ecc.c79 * @base_reg: IO base address of OCS ECC
87 void __iomem *base_reg; member in struct:ocs_ecc_dev
137 return readl_poll_timeout((dev->base_reg + HW_OFFS_OCS_ECC_STATUS),
146 ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
156 iowrite32(op_size | inst, dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
159 memcpy_toio(dev->base_reg + HW_OFFS_OCS_ECC_DATA_IN, data_in,
169 iowrite32(ECC_ENABLE_INTR, ecc_dev->base_reg + HW_OFFS_OCS_ECC_IER);
170 iowrite32(op_size | inst, ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
185 memcpy_fromio(cx_out, dev->base_reg + HW_OFFS_OCS_ECC_CX_DATA_OUT,
199 memcpy_fromio(cy_out, dev->base_reg
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H A Docs-aes.h40 * @base_reg: IO base address of OCS AES.
49 void __iomem *base_reg; member in struct:ocs_aes_dev
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c1955 const u64 base_reg)
1959 WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK);
1961 rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
1967 base_reg);
1975 u64 base_reg; local
1985 base_reg = debug_stm_regs[params->reg_idx];
1990 if (!base_reg)
1997 read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);
2001 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2011 WREG32(base_reg
1954 gaudi2_unlock_coresight_unit(struct hl_device *hdev, const u64 base_reg) argument
2062 u64 base_reg; local
2302 u64 base_reg; local
2342 u64 base_reg; local
2443 u64 base_reg; local
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/linux-master/arch/arm/mach-omap1/
H A Dirq.c58 unsigned long base_reg; member in struct:omap_irq_bank
116 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
117 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
120 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
121 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
128 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
129 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
130 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
131 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
208 irq_banks[i].va = ioremap(irq_banks[i].base_reg,
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/linux-master/drivers/watchdog/
H A Drdc321x_wdt.c51 int base_reg; member in struct:__anon2921
67 rdc321x_wdt_device.base_reg, &val);
70 rdc321x_wdt_device.base_reg, val);
99 rdc321x_wdt_device.base_reg, RDC_CLS_TMR);
103 rdc321x_wdt_device.base_reg,
159 rdc321x_wdt_device.base_reg, &value);
233 rdc321x_wdt_device.base_reg = r->start;
247 rdc321x_wdt_device.base_reg, RDC_WDT_RST);
/linux-master/sound/soc/codecs/
H A Dmadera.h215 #define MADERA_MUX_ENUMS(name, base_reg) \
216 static MADERA_MUX_ENUM_DECL(name##_enum, base_reg); \
219 #define MADERA_MIXER_ENUMS(name, base_reg) \
220 MADERA_MUX_ENUMS(name##_in1, base_reg); \
221 MADERA_MUX_ENUMS(name##_in2, base_reg + 2); \
222 MADERA_MUX_ENUMS(name##_in3, base_reg + 4); \
223 MADERA_MUX_ENUMS(name##_in4, base_reg + 6)
225 #define MADERA_DSP_AUX_ENUMS(name, base_reg) \
226 MADERA_MUX_ENUMS(name##_aux1, base_reg); \
227 MADERA_MUX_ENUMS(name##_aux2, base_reg
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H A Darizona.h168 #define ARIZONA_MUX_ENUMS(name, base_reg) \
169 static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \
172 #define ARIZONA_MIXER_ENUMS(name, base_reg) \
173 ARIZONA_MUX_ENUMS(name##_in1, base_reg); \
174 ARIZONA_MUX_ENUMS(name##_in2, base_reg + 2); \
175 ARIZONA_MUX_ENUMS(name##_in3, base_reg + 4); \
176 ARIZONA_MUX_ENUMS(name##_in4, base_reg + 6)
178 #define ARIZONA_DSP_AUX_ENUMS(name, base_reg) \
179 ARIZONA_MUX_ENUMS(name##_aux1, base_reg); \
180 ARIZONA_MUX_ENUMS(name##_aux2, base_reg
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/linux-master/drivers/clk/
H A Dclk-en7523.c29 u32 base_reg; member in struct:en_clk_desc
61 .base_reg = REG_GSW_CLK_DIV_SEL,
74 .base_reg = REG_EMI_CLK_DIV_SEL,
87 .base_reg = REG_BUS_CLK_DIV_SEL,
100 .base_reg = REG_SPI_CLK_FREQ_SEL,
115 .base_reg = REG_SPI_CLK_DIV_SEL,
127 .base_reg = REG_NPU_CLK_DIV_SEL,
140 .base_reg = REG_CRYPTO_CLKSRC,
161 val = readl(base + desc->base_reg);
179 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
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/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c116 u32 base_reg; local
123 base_reg = SUN8I_CSC_COEFF(base, 0);
124 regmap_bulk_write(map, base_reg, table, 12);
129 base_reg = SUN8I_CSC_COEFF(base, i + 1);
131 base_reg = SUN8I_CSC_COEFF(base, i - 1);
133 base_reg = SUN8I_CSC_COEFF(base, i);
134 regmap_write(map, base_reg, table[i]);
/linux-master/drivers/media/dvb-frontends/
H A Ddibx000_common.c82 while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
105 dibx000_read_word(mst, mst->base_reg + 2);
112 dibx000_write_word(mst, mst->base_reg, data);
129 dibx000_write_word(mst, mst->base_reg+1, da);
161 dibx000_write_word(mst, mst->base_reg+1, da);
169 da = dibx000_read_word(mst, mst->base_reg);
188 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
204 return dibx000_write_word(mst, mst->base_reg + 4, intf);
277 tx[0] = (((mst->base_reg + 1) >> 8) & 0xff);
278 tx[1] = ((mst->base_reg
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/linux-master/drivers/clk/visconti/
H A Dpll.h52 unsigned long base_reg; member in struct:visconti_pll_info
/linux-master/tools/testing/selftests/powerpc/include/
H A Dbasic_asm.h97 .macro OP_REGS op, reg_width, start_reg, end_reg, base_reg, base_reg_offset=0, skip=0 variable
100 \op i, (\reg_width * (i - \skip) + \base_reg_offset)(\base_reg)
/linux-master/arch/mips/kernel/
H A Dmips-cm.c203 u32 base_reg; local
209 base_reg = read_gcr_l2_only_sync_base();
210 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
211 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
243 u32 base_reg; local
263 base_reg = read_gcr_base();
264 if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
/linux-master/sound/soc/cirrus/
H A Dep93xx-i2s.c110 unsigned base_reg; local
125 base_reg = EP93XX_I2S_TX0EN;
127 base_reg = EP93XX_I2S_RX0EN;
128 ep93xx_i2s_write_reg(info, base_reg, 1);
140 unsigned base_reg; local
149 base_reg = EP93XX_I2S_TX0EN;
151 base_reg = EP93XX_I2S_RX0EN;
152 ep93xx_i2s_write_reg(info, base_reg, 0);
/linux-master/drivers/bus/
H A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c47 * @base_reg: base of scratch bits
52 int base_reg, unsigned int offset,
55 int reg = base_reg + (offset / 8);
72 * @base_reg: base of scratch bits
79 int base_reg, unsigned int offset,
82 int reg = base_reg + (offset / 8);
51 mv88e6xxx_g2_scratch_get_bit(struct mv88e6xxx_chip *chip, int base_reg, unsigned int offset, int *set) argument
78 mv88e6xxx_g2_scratch_set_bit(struct mv88e6xxx_chip *chip, int base_reg, unsigned int offset, int set) argument
/linux-master/drivers/input/keyboard/
H A Dtm2-touchkey.c38 u8 base_reg; member in struct:touchkey_variant
58 .base_reg = 0x00,
65 .base_reg = 0x00,
79 .base_reg = 0x00,
107 touchkey->variant->base_reg, data);

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