intel/keembay/ocs-aes.c

206 	iowrite32(0x7FF, aes_dev->base_reg + AES_BYTE_ORDER_CFG_OFFSET);
212 	iowrite32(AES_ACTIVE_TRIGGER, aes_dev->base_reg + AES_ACTIVE_OFFSET);
219 		  aes_dev->base_reg + AES_ACTIVE_OFFSET);
234 		  aes_dev->base_reg + AES_ACTIVE_OFFSET);
243 		aes_active_reg = ioread32(aes_dev->base_reg +
254 		reg = ioread32(aes_dev->base_reg + AES_A_DMA_STATUS_OFFSET);
268 		  aes_dev->base_reg + AES_ACTIVE_OFFSET);
274 	iowrite32(0, aes_dev->base_reg + AES_A_DMA_SRC_SIZE_OFFSET);
275 	iowrite32(0, aes_dev->base_reg + AES_A_DMA_DST_SIZE_OFFSET);
282 		  aes_dev->base_reg + AES_A_DMA_DMA_MODE_OFFSET);
290 		  aes_dev->base_reg + AES_A_DMA_DMA_MODE_OFFSET);
298 		  aes_dev->base_reg + AES_A_DMA_DMA_MODE_OFFSET);
307 		  aes_dev->base_reg + AES_A_DMA_DMA_MODE_OFFSET);
313 	iowrite32(0x00000000, aes_dev->base_reg + AES_A_DMA_PERF_CNTR_OFFSET);
315 		  aes_dev->base_reg + AES_A_DMA_WHILE_ACTIVE_MODE_OFFSET);
322 	while (ioread32(aes_dev->base_reg + AES_A_DMA_PERF_CNTR_OFFSET) < delay)
325 		  aes_dev->base_reg + AES_A_DMA_WHILE_ACTIVE_MODE_OFFSET);
335 		  aes_dev->base_reg + AES_A_DMA_MSI_IER_OFFSET);
336 	iowrite32(AES_DISABLE_INT, aes_dev->base_reg + AES_IER_OFFSET);
339 	isr_val = ioread32(aes_dev->base_reg + AES_A_DMA_MSI_ISR_OFFSET);
342 			  aes_dev->base_reg + AES_A_DMA_MSI_ISR_OFFSET);
344 	isr_val = ioread32(aes_dev->base_reg + AES_A_DMA_MSI_MASK_OFFSET);
347 			  aes_dev->base_reg + AES_A_DMA_MSI_MASK_OFFSET);
349 	isr_val = ioread32(aes_dev->base_reg + AES_ISR_OFFSET);
351 		iowrite32(isr_val, aes_dev->base_reg + AES_ISR_OFFSET);
366 			  aes_dev->base_reg + AES_A_DMA_MSI_IER_OFFSET);
375 		iowrite32(AES_COMPLETE_INT, aes_dev->base_reg + AES_IER_OFFSET);
380 		iowrite32(AES_DISABLE_INT, aes_dev->base_reg + AES_IER_OFFSET);
403 			  aes_dev->base_reg + AES_A_DMA_MSI_IER_OFFSET);
425 	iowrite32(0, aes_dev->base_reg + AES_A_DMA_SRC_SIZE_OFFSET);
427 		  aes_dev->base_reg + AES_A_DMA_NEXT_SRC_DESCR_OFFSET);
434 	iowrite32(0, aes_dev->base_reg + AES_A_DMA_DST_SIZE_OFFSET);
436 		  aes_dev->base_reg + AES_A_DMA_NEXT_DST_DESCR_OFFSET);
445 	aes_dma_isr = ioread32(aes_dev->base_reg + AES_A_DMA_MSI_ISR_OFFSET);
507 			  aes_dev->base_reg + AES_KEY_0_OFFSET +
518 	iowrite32(val, aes_dev->base_reg + AES_KEY_SIZE_OFFSET);
556 	iowrite32(val, aes_dev->base_reg + AES_COMMAND_OFFSET);
593 	iowrite32(val, aes_dev->base_reg + AES_PLEN_OFFSET);
833 		iowrite32(iv32[0], aes_dev->base_reg + AES_IV_0_OFFSET);
834 		iowrite32(iv32[1], aes_dev->base_reg + AES_IV_1_OFFSET);
835 		iowrite32(iv32[2], aes_dev->base_reg + AES_IV_2_OFFSET);
836 		iowrite32(iv32[3], aes_dev->base_reg + AES_IV_3_OFFSET);
865 		iv32[0] = ioread32(aes_dev->base_reg + AES_IV_0_OFFSET);
866 		iv32[1] = ioread32(aes_dev->base_reg + AES_IV_1_OFFSET);
867 		iv32[2] = ioread32(aes_dev->base_reg + AES_IV_2_OFFSET);
868 		iv32[3] = ioread32(aes_dev->base_reg + AES_IV_3_OFFSET);
884 	iowrite32(0x00000001, aes_dev->base_reg + AES_IV_0_OFFSET);
885 	iowrite32(__swab32(j0[2]), aes_dev->base_reg + AES_IV_1_OFFSET);
886 	iowrite32(__swab32(j0[1]), aes_dev->base_reg + AES_IV_2_OFFSET);
887 	iowrite32(__swab32(j0[0]), aes_dev->base_reg + AES_IV_3_OFFSET);
901 	tag_u32[0] = __swab32(ioread32(aes_dev->base_reg + AES_T_MAC_3_OFFSET));
902 	tag_u32[1] = __swab32(ioread32(aes_dev->base_reg + AES_T_MAC_2_OFFSET));
903 	tag_u32[2] = __swab32(ioread32(aes_dev->base_reg + AES_T_MAC_1_OFFSET));
904 	tag_u32[3] = __swab32(ioread32(aes_dev->base_reg + AES_T_MAC_0_OFFSET));
955 	iowrite32(tag_size, aes_dev->base_reg + AES_TLEN_OFFSET);
963 	iowrite32(val, aes_dev->base_reg + AES_MULTIPURPOSE2_0_OFFSET);
965 	iowrite32(val, aes_dev->base_reg + AES_MULTIPURPOSE2_1_OFFSET);
970 	iowrite32(val, aes_dev->base_reg + AES_MULTIPURPOSE2_2_OFFSET);
972 	iowrite32(val, aes_dev->base_reg + AES_MULTIPURPOSE2_3_OFFSET);
1042 		iowrite8(in_tag[i], aes_dev->base_reg +
1114 		iowrite8(b0[i], aes_dev->base_reg +
1155 			 aes_dev->base_reg +
1278 		tag[i] = ioread32(aes_dev->base_reg +
1280 		yr[i] = ioread32(aes_dev->base_reg +
1345 		  aes_dev->base_reg + AES_MULTIPURPOSE1_3_OFFSET);
1347 		  aes_dev->base_reg + AES_MULTIPURPOSE1_2_OFFSET);
1349 		  aes_dev->base_reg + AES_MULTIPURPOSE1_1_OFFSET);
1351 		  aes_dev->base_reg + AES_MULTIPURPOSE1_0_OFFSET);
1354 	iowrite32(tag_size, aes_dev->base_reg + AES_TLEN_OFFSET);