Searched refs:acr (Results 1 - 25 of 58) sorted by relevance

123

/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
H A Dbase.c33 nvkm_acr_hsfw_find(struct nvkm_acr *acr, const char *name) argument
37 list_for_each_entry(hsfw, &acr->hsfw, head) {
46 nvkm_acr_hsfw_boot(struct nvkm_acr *acr, const char *name) argument
48 struct nvkm_subdev *subdev = &acr->subdev;
51 hsfw = nvkm_acr_hsfw_find(acr, name);
60 nvkm_acr_rtos(struct nvkm_acr *acr) argument
64 if (acr) {
65 list_for_each_entry(lsf, &acr->lsf, head) {
75 nvkm_acr_unload(struct nvkm_acr *acr) argument
77 if (acr
89 nvkm_acr_load(struct nvkm_acr *acr) argument
128 nvkm_acr_reload(struct nvkm_acr *acr) argument
137 struct nvkm_acr *acr = device->acr; local
174 struct nvkm_acr *acr = device->acr; local
197 struct nvkm_acr *acr = nvkm_acr(subdev); local
206 nvkm_acr_cleanup(struct nvkm_acr *acr) argument
218 struct nvkm_acr *acr = nvkm_acr(subdev); local
362 struct nvkm_acr *acr = nvkm_acr(subdev); local
396 nvkm_acr_ctor_wpr(struct nvkm_acr *acr, int ver) argument
422 struct nvkm_acr *acr; local
[all...]
H A Dgp102.c29 #include <nvfw/acr.h>
33 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) argument
41 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
42 wpr_header_v1_dump(&acr->subdev, &hdr);
44 list_for_each_entry(lsfw, &acr->lsfw, head) {
48 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
49 lsb_header_v1_dump(&acr->subdev, &lsb);
51 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
62 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) argument
72 nvkm_wobj(acr
77 gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) argument
119 gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) argument
134 gp102_acr_wpr_layout(struct nvkm_acr *acr) argument
163 gp102_acr_wpr_parse(struct nvkm_acr *acr) argument
200 struct nvkm_acr *acr = fw->falcon->owner->device->acr; local
257 gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) argument
[all...]
H A Dgm20b.c29 #include <nvfw/acr.h>
33 gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) argument
35 struct nvkm_subdev *subdev = &acr->subdev;
37 acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end);
39 if ((acr->wpr_end - acr->wpr_start) < wpr_size) {
45 wpr_size, 0, true, &acr
73 struct nvkm_acr *acr = fw->falcon->owner->device->acr; local
115 gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) argument
[all...]
H A Dga100.c25 ga100_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit) argument
27 struct nvkm_device *device = acr->subdev.device;
35 ga100_acr_hsfw_ctor(struct nvkm_acr *acr, const char *bl, const char *fw, argument
46 list_add_tail(&hsfw->head, &acr->hsfw);
48 return nvkm_falcon_fw_ctor_hs_v2(fwif->func, name, &acr->subdev, fw, ver, NULL, &hsfw->fw);
H A Dtu102.c30 #include <nvfw/acr.h>
33 tu102_acr_init(struct nvkm_acr *acr) argument
35 int ret = nvkm_acr_hsfw_boot(acr, "AHESASC");
39 return nvkm_acr_hsfw_boot(acr, "ASB");
43 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) argument
50 nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
53 list_for_each_entry(lsfw, &acr->lsfw, head) {
65 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
69 ret = gp102_acr_wpr_build_lsb(acr, lsfw);
74 nvkm_wobj(acr
88 tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw, const char *name, int version, const struct nvkm_acr_hsf_fwif *fwif) argument
167 tu102_acr_load(struct nvkm_acr *acr, int version, const struct nvkm_acr_fwif *fwif) argument
[all...]
H A Dgm200.c32 #include <nvfw/acr.h>
40 gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) argument
42 nvkm_warn(&acr->subdev, "firmware unavailable\n");
47 gm200_acr_init(struct nvkm_acr *acr) argument
49 return nvkm_acr_hsfw_boot(acr, "load");
53 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit) argument
55 struct nvkm_device *device = acr->subdev.device;
65 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) argument
67 struct nvkm_subdev *subdev = &acr->subdev;
74 nvkm_robj(acr
114 gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) argument
129 gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) argument
169 gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) argument
183 gm200_acr_wpr_layout(struct nvkm_acr *acr) argument
209 gm200_acr_wpr_parse(struct nvkm_acr *acr) argument
245 gm200_acr_hsfw_ctor(struct nvkm_acr *acr, const char *bl, const char *fw, const char *name, int ver, const struct nvkm_acr_hsf_fwif *fwif) argument
285 struct nvkm_acr *acr = fw->falcon->owner->device->acr; local
343 gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) argument
[all...]
H A Dga102.c25 #include <nvfw/acr.h>
28 ga102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) argument
40 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
41 wpr_header_v2_dump(&acr->subdev, &hdr);
43 list_for_each_entry(lsfw, &acr->lsfw, head) {
47 nvkm_robj(acr->wpr, hdr.wpr.lsb_offset, lsb, sizeof(*lsb));
48 lsb_header_v2_dump(&acr->subdev, lsb);
50 lsfw->func->bld_patch(acr, lsb->bl_data_off, adjust);
62 ga102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) argument
114 ret = nvkm_falcon_get(fw.falcon, &acr
133 ga102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) argument
189 ga102_acr_wpr_layout(struct nvkm_acr *acr) argument
218 ga102_acr_wpr_parse(struct nvkm_acr *acr) argument
291 ga102_acr_load(struct nvkm_acr *acr, int version, const struct nvkm_acr_fwif *fwif) argument
[all...]
H A Dlsfw.c39 nvkm_acr_lsfw_del_all(struct nvkm_acr *acr) argument
42 list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) {
48 nvkm_acr_lsfw_get(struct nvkm_acr *acr, enum nvkm_acr_lsf_id id) argument
51 list_for_each_entry(lsfw, &acr->lsfw, head) {
59 nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr, argument
64 if (!acr || list_empty(&acr->hsfw))
67 lsfw = nvkm_acr_lsfw_get(acr, id);
69 nvkm_error(&acr->subdev, "LSFW %d redefined\n", id);
78 list_add_tail(&lsfw->head, &acr
94 struct nvkm_acr *acr = subdev->device->acr; local
255 struct nvkm_acr *acr = subdev->device->acr; local
333 struct nvkm_acr *acr = subdev->device->acr; local
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgp108.c24 #include <subdev/acr.h>
29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
32 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
35 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
36 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
40 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
56 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
H A Dgm20b.c26 #include <subdev/acr.h>
34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
52 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
70 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
87 if (!device->acr) {
H A Dgm200.c28 #include <subdev/acr.h>
46 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
49 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
52 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
53 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
57 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
73 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
H A Dgp10b.c26 #include <subdev/acr.h>
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dgp108.c23 #include <subdev/acr.h>
H A Dgp102.c25 #include <subdev/acr.h>
78 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
81 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
85 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
86 loader_config_v1_dump(&acr->subdev, &hdr);
90 gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
107 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
241 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
244 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
247 nvkm_wobj(acr
252 gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld, struct nvkm_acr_lsfw *lsfw) argument
[all...]
H A Dpriv.h26 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_sec2_fwif
H A Dtu102.c23 #include <subdev/acr.h>
/linux-master/arch/arm/mach-omap2/
H A Domap-smp.c77 u32 acr, revidr; local
85 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
94 if ((acr & acr_mask) == acr_mask)
97 acr |= acr_mask;
98 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
123 u32 acr, acr_mask; local
125 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
133 if ((acr & acr_mask) == acr_mask)
136 acr |= acr_mask;
137 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
[all...]
H A Domap-secure.c192 u32 acr; local
195 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
196 acr &= ~clear_bits;
197 acr |= set_bits;
202 1, acr, 0, 0, 0);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c25 #include <subdev/acr.h>
66 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) argument
71 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
81 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
83 loader_config_dump(&acr->subdev, &hdr);
87 gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld, argument
109 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
255 ver, fwif->acr);
H A Dgp10b.c24 #include <subdev/acr.h>
/linux-master/sound/soc/sh/
H A Ddma-sh7760.c214 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); local
216 BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD;
221 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); local
223 BRGREG(BRGACR) = acr | ACR_TDS;
228 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); local
230 BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD;
235 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); local
237 BRGREG(BRGACR) = acr | ACR_RDS;
/linux-master/drivers/gpu/drm/radeon/
H A Ddce3_1_afmt.c172 const struct radeon_hdmi_acr *acr)
182 HDMI0_ACR_CTS_32(acr->cts_32khz),
185 HDMI0_ACR_N_32(acr->n_32khz),
189 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
192 HDMI0_ACR_N_44(acr->n_44_1khz),
196 HDMI0_ACR_CTS_48(acr->cts_48khz),
199 HDMI0_ACR_N_48(acr->n_48khz),
171 dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, const struct radeon_hdmi_acr *acr) argument
H A Dr600.h51 const struct radeon_hdmi_acr *acr);
H A Dradeon_audio.h57 const struct radeon_hdmi_acr *acr);
93 const struct radeon_hdmi_acr *acr);
H A Devergreen_hdmi.h46 const struct radeon_hdmi_acr *acr);

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