1/*
2 * Copyright 2019 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "priv.h"
23#include <subdev/acr.h>
24#include <subdev/gsp.h>
25
26#include <nvfw/sec2.h>
27
28static const struct nvkm_falcon_func
29tu102_sec2_flcn = {
30	.disable = gm200_flcn_disable,
31	.enable = gm200_flcn_enable,
32	.reset_pmc = true,
33	.reset_eng = gp102_flcn_reset_eng,
34	.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
35	.debug = 0x408,
36	.bind_inst = gm200_flcn_bind_inst,
37	.bind_stat = gm200_flcn_bind_stat,
38	.bind_intr = true,
39	.imem_pio = &gm200_flcn_imem_pio,
40	.dmem_pio = &gm200_flcn_dmem_pio,
41	.emem_addr = 0x01000000,
42	.emem_pio = &gp102_flcn_emem_pio,
43	.start = nvkm_falcon_v1_start,
44	.cmdq = { 0xc00, 0xc04, 8 },
45	.msgq = { 0xc80, 0xc84, 8 },
46};
47
48static const struct nvkm_sec2_func
49tu102_sec2 = {
50	.flcn = &tu102_sec2_flcn,
51	.unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
52	.unit_acr = NV_SEC2_UNIT_V2_ACR,
53	.intr = gp102_sec2_intr,
54	.initmsg = gp102_sec2_initmsg,
55};
56
57MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
58MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
59MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
60MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin");
61MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin");
62MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin");
63MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin");
64MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin");
65MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin");
66MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin");
67MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin");
68MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin");
69MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin");
70MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin");
71MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
72
73static const struct nvkm_sec2_fwif
74tu102_sec2_fwif[] = {
75	{  0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
76	{ -1, gp102_sec2_nofw, &tu102_sec2 }
77};
78
79int
80tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
81	       struct nvkm_sec2 **psec2)
82{
83	/* TOP info wasn't updated on Turing to reflect the PRI
84	 * address change for some reason.  We override it here.
85	 */
86	const u32 addr = 0x840000;
87
88	if (nvkm_gsp_rm(device->gsp))
89		return r535_sec2_new(&tu102_sec2, device, type, inst, addr, psec2);
90
91	return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, addr, psec2);
92}
93