Searched refs:__raw_writeq (Results 1 - 25 of 57) sorted by relevance

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/linux-master/arch/mips/sibyte/common/
H A Dsb_tbprof.c152 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
161 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
165 __raw_writeq(
171 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
178 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
180 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
185 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
199 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
221 __raw_writeq(M_SCD_TRACE_CFG_RESET,
232 __raw_writeq(M_SCD_TRACE_CFG_RESE
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/linux-master/include/linux/mlx5/
H A Ddoorbell.h53 __raw_writeq(*(u64 *)val, dest);
/linux-master/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c360 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
363 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
364 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
391 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
399 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
400 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
401 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
453 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
458 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
460 __raw_writeq(M_MAC_MDIO_DIR_INPU
[all...]
/linux-master/arch/mips/kernel/
H A Dcevt-bcm1480.c39 __raw_writeq(0, cfg);
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
53 __raw_writeq(0, cfg);
65 __raw_writeq(0, cfg);
66 __raw_writeq(delta - 1, init);
67 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
129 __raw_writeq(IMR_IP4_VAL,
H A Dcevt-sb1250.c36 __raw_writeq(0, cfg);
49 __raw_writeq(0, cfg);
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
51 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
64 __raw_writeq(0, cfg);
65 __raw_writeq(delta - 1, init);
66 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
129 __raw_writeq(IMR_IP4_VAL,
H A Dcsrc-sb1250.c58 __raw_writeq(0,
61 __raw_writeq(SB1250_HPT_VALUE,
64 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
/linux-master/arch/mips/include/asm/
H A Dfb.h31 __raw_writeq(b, addr);
/linux-master/include/asm-generic/
H A Dlogic_io.h63 #define __raw_writeq __raw_writeq macro
64 void __raw_writeq(u64 value, volatile void __iomem *addr);
H A Dfb.h102 #if defined(__raw_writeq)
105 __raw_writeq(b, addr);
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_pio_copy.c53 __raw_writeq(*src++, dst++);
/linux-master/arch/mips/sibyte/bcm1480/
H A Dirq.c168 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
172 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
248 __raw_writeq(IMR_IP2_VAL,
257 __raw_writeq(IMR_IP2_VAL,
271 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
278 __raw_writeq(0xffffffffffffffffULL,
280 __raw_writeq(0xffffffffffffffffULL,
288 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
292 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
H A Dsmp.c69 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
169 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
/linux-master/arch/mips/sibyte/swarm/
H A Drtc_m41t81.c88 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
89 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
95 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
103 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
115 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
116 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
117 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
125 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
H A Drtc_xicor1241.c63 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
64 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
65 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
71 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
79 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
91 __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
92 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
93 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
101 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
/linux-master/arch/mips/sibyte/sb1250/
H A Dirq.c155 __raw_writeq(pending,
230 __raw_writeq(IMR_IP2_VAL,
234 __raw_writeq(IMR_IP2_VAL,
247 __raw_writeq(IMR_IP3_VAL,
250 __raw_writeq(IMR_IP3_VAL,
255 __raw_writeq(0xffffffffffffffffULL,
257 __raw_writeq(0xffffffffffffffffULL,
262 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
263 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
/linux-master/drivers/infiniband/hw/mthca/
H A Dmthca_doorbell.h56 __raw_writeq((__force u64) val, dest);
62 __raw_writeq((__force u64) cpu_to_be64((u64) hi << 32 | lo), dest);
/linux-master/arch/arm64/kernel/
H A Dio.c53 __raw_writeq(*(u64 *)from, to);
86 __raw_writeq(qc, dst);
/linux-master/arch/loongarch/kernel/
H A Dio.c50 __raw_writeq(*(u64 *)from, to);
83 __raw_writeq(qc, dst);
/linux-master/include/linux/mlx4/
H A Ddoorbell.h58 __raw_writeq(*(u64 *) val, dest);
/linux-master/arch/arm64/include/asm/
H A Dio.h45 #define __raw_writeq __raw_writeq macro
46 static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) function
164 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
/linux-master/lib/
H A Diomap_copy.c73 __raw_writeq(*src++, dst++);
/linux-master/arch/s390/include/asm/
H A Dio.h74 #define __raw_writeq zpci_write_u64 macro
/linux-master/arch/mips/sgi-ip27/
H A Dip27-irq.c58 __raw_writeq(mask[0], hd->irq_mask[0]);
59 __raw_writeq(mask[1], hd->irq_mask[1]);
68 __raw_writeq(mask[0], hd->irq_mask[0]);
69 __raw_writeq(mask[1], hd->irq_mask[1]);
/linux-master/arch/riscv/include/asm/
H A Dmmio.h38 #define __raw_writeq __raw_writeq macro
39 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) function
98 #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
/linux-master/drivers/i2c/busses/
H A Di2c-octeon-core.h127 __raw_writeq(val, addr);
144 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
172 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));

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