1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h 4 * which was based on arch/arm/include/io.h 5 * 6 * Copyright (C) 1996-2000 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 * Copyright (C) 2014 Regents of the University of California 9 */ 10 11#ifndef _ASM_RISCV_MMIO_H 12#define _ASM_RISCV_MMIO_H 13 14#include <linux/types.h> 15#include <asm/fence.h> 16#include <asm/mmiowb.h> 17 18/* Generic IO read/write. These perform native-endian accesses. */ 19#define __raw_writeb __raw_writeb 20static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 21{ 22 asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); 23} 24 25#define __raw_writew __raw_writew 26static inline void __raw_writew(u16 val, volatile void __iomem *addr) 27{ 28 asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); 29} 30 31#define __raw_writel __raw_writel 32static inline void __raw_writel(u32 val, volatile void __iomem *addr) 33{ 34 asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); 35} 36 37#ifdef CONFIG_64BIT 38#define __raw_writeq __raw_writeq 39static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 40{ 41 asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); 42} 43#endif 44 45#define __raw_readb __raw_readb 46static inline u8 __raw_readb(const volatile void __iomem *addr) 47{ 48 u8 val; 49 50 asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); 51 return val; 52} 53 54#define __raw_readw __raw_readw 55static inline u16 __raw_readw(const volatile void __iomem *addr) 56{ 57 u16 val; 58 59 asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); 60 return val; 61} 62 63#define __raw_readl __raw_readl 64static inline u32 __raw_readl(const volatile void __iomem *addr) 65{ 66 u32 val; 67 68 asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); 69 return val; 70} 71 72#ifdef CONFIG_64BIT 73#define __raw_readq __raw_readq 74static inline u64 __raw_readq(const volatile void __iomem *addr) 75{ 76 u64 val; 77 78 asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); 79 return val; 80} 81#endif 82 83/* 84 * Unordered I/O memory access primitives. These are even more relaxed than 85 * the relaxed versions, as they don't even order accesses between successive 86 * operations to the I/O regions. 87 */ 88#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) 89#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) 90#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) 91 92#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) 93#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) 94#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) 95 96#ifdef CONFIG_64BIT 97#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) 98#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) 99#endif 100 101/* 102 * Relaxed I/O memory access primitives. These follow the Device memory 103 * ordering rules but do not guarantee any ordering relative to Normal memory 104 * accesses. These are defined to order the indicated access (either a read or 105 * write) with all other I/O memory accesses to the same peripheral. Since the 106 * platform specification defines that all I/O regions are strongly ordered on 107 * channel 0, no explicit fences are required to enforce this ordering. 108 */ 109/* FIXME: These are now the same as asm-generic */ 110#define __io_rbr() do {} while (0) 111#define __io_rar() do {} while (0) 112#define __io_rbw() do {} while (0) 113#define __io_raw() do {} while (0) 114 115#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) 116#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) 117#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) 118 119#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) 120#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) 121#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) 122 123#ifdef CONFIG_64BIT 124#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) 125#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) 126#endif 127 128/* 129 * I/O memory access primitives. Reads are ordered relative to any following 130 * Normal memory read and delay() loop. Writes are ordered relative to any 131 * prior Normal memory write. The memory barriers here are necessary as RISC-V 132 * doesn't define any ordering between the memory space and the I/O space. 133 */ 134#define __io_br() do {} while (0) 135#define __io_ar(v) RISCV_FENCE(i, ir) 136#define __io_bw() RISCV_FENCE(w, o) 137#define __io_aw() mmiowb_set_pending() 138 139#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) 140#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) 141#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) 142 143#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) 144#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) 145#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) 146 147#ifdef CONFIG_64BIT 148#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) 149#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); }) 150#endif 151 152#endif /* _ASM_RISCV_MMIO_H */ 153